JPS6480078A - Vertical field-effect transistor - Google Patents

Vertical field-effect transistor

Info

Publication number
JPS6480078A
JPS6480078A JP23767687A JP23767687A JPS6480078A JP S6480078 A JPS6480078 A JP S6480078A JP 23767687 A JP23767687 A JP 23767687A JP 23767687 A JP23767687 A JP 23767687A JP S6480078 A JPS6480078 A JP S6480078A
Authority
JP
Japan
Prior art keywords
film
regions
grown
resist
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23767687A
Other languages
Japanese (ja)
Inventor
Takatoshi Fujimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP23767687A priority Critical patent/JPS6480078A/en
Publication of JPS6480078A publication Critical patent/JPS6480078A/en
Pending legal-status Critical Current

Links

Landscapes

  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To bring the source electrode into contact with the base regions easily without fail by a method wherein a groove reaching the base region is formed in the source region passing through the source region. CONSTITUTION:An SiO2 film 2 is grown on a substrate 1 and then polycrystalline Si 3 is grown on the SiO2 film 2. First, impurity is ion-implanted in the substrate 1 using the polycrystalline Si 3 as a mask to form base regions 4 and source regions 5. Second, an interlayer insulating film 7 is grown and then the film 7 and the film 2 are anisotropically etched away using a resist 8 coated on the film 7 as a mask. Furthermore, the substrate 1 is anisotropically etched away to form a groove 11 shallower than the regions 4 but deeper than the regions 5. Third, the film 7 and the film 2 are isotropically etched away using the resist 8 as a mask. Finally, the resist 8 is removed to form source electrodes.
JP23767687A 1987-09-21 1987-09-21 Vertical field-effect transistor Pending JPS6480078A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23767687A JPS6480078A (en) 1987-09-21 1987-09-21 Vertical field-effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23767687A JPS6480078A (en) 1987-09-21 1987-09-21 Vertical field-effect transistor

Publications (1)

Publication Number Publication Date
JPS6480078A true JPS6480078A (en) 1989-03-24

Family

ID=17018856

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23767687A Pending JPS6480078A (en) 1987-09-21 1987-09-21 Vertical field-effect transistor

Country Status (1)

Country Link
JP (1) JPS6480078A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007115734A (en) * 2005-10-18 2007-05-10 Nec Electronics Corp Method of manufacturing semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6021571A (en) * 1983-07-15 1985-02-02 Tdk Corp Semiconductor device and manufacture thereof

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6021571A (en) * 1983-07-15 1985-02-02 Tdk Corp Semiconductor device and manufacture thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007115734A (en) * 2005-10-18 2007-05-10 Nec Electronics Corp Method of manufacturing semiconductor device
US7514307B2 (en) 2005-10-18 2009-04-07 Nec Electronics Corporation Method of manufacturing a semiconductor apparatus

Similar Documents

Publication Publication Date Title
KR900003840B1 (en) Insulation gate field effect transistor manufacturing method
EP0236123A3 (en) A semiconductor device and method for preparing the same
EP0148595A3 (en) Method of fabricating mesa mosfet using overhang mask and resulting structure
JPS6480078A (en) Vertical field-effect transistor
JPS5691470A (en) Semiconductor
JPS572519A (en) Manufacture of semiconductor device
JPS5688362A (en) Vertical type power mos transistor
JPS6420663A (en) Manufacture of semiconductor device
JPS5688356A (en) Manufacture of memory cell
JPS5372474A (en) Manufacture for field effect transistor
JPS55162270A (en) Semiconductor device
JPS52117079A (en) Preparation of semiconductor device
JPS5561069A (en) Manufacture of semiconductor device
JPS5670669A (en) Longitudinal semiconductor device
JPS5561070A (en) Semiconductor device
JPS5658258A (en) Semiconductor integrated circuit
JPS5739579A (en) Mos semiconductor device and manufacture thereof
JPS5690608A (en) Differential amplifier using mis transistor with v type channel
JPS6427265A (en) Manufacture of semiconductor device
JPS57132357A (en) Manufacture of semiconductor element
JPS586139A (en) Manufacture of semiconductor device
JPS645066A (en) Manufacture of field effect transistor
JPS5559775A (en) Method of fabricating semiconductor device
JPS5721866A (en) Manufacture of insulated gate type field effect transistor
KR930001480A (en) Structure and manufacturing method of trench buried LDD MOSFET