JPS647520A - Manufacture of integrated circuit - Google Patents

Manufacture of integrated circuit

Info

Publication number
JPS647520A
JPS647520A JP62163758A JP16375887A JPS647520A JP S647520 A JPS647520 A JP S647520A JP 62163758 A JP62163758 A JP 62163758A JP 16375887 A JP16375887 A JP 16375887A JP S647520 A JPS647520 A JP S647520A
Authority
JP
Japan
Prior art keywords
pattern
exposing method
light
productivity
exposure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62163758A
Other languages
Japanese (ja)
Other versions
JPH0548927B2 (en
Inventor
Yukinori Ochiai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62163758A priority Critical patent/JPS647520A/en
Publication of JPS647520A publication Critical patent/JPS647520A/en
Publication of JPH0548927B2 publication Critical patent/JPH0548927B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/7045—Hybrid exposures, i.e. multiple exposures of the same area using different types of exposure apparatus, e.g. combining projection, proximity, direct write, interferometric, UV, x-ray or particle beam

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Electron Beam Exposure (AREA)

Abstract

PURPOSE:To enhance productivity as well as to make it possible to form a microscopic pattern by a method wherein, using a light-exposing method having high productivity by conducting a collective exposure on the pattern in excess of its degree of resolution, and a focussed ion beam exposing method is used for the microscopic patterns which can not be exposed by the light-exposing method. CONSTITUTION:Productivity is enhance using a lightly productive light-exposing method for the exposure of the pattern having relatively large patterns in excess of the degree of resolution the light-exposing method by conducting a collective exposure using a mask even through its degree of resolution is low. Also, a focussed ion beam exposing method, having excellent degree of resolution although it has low productivity, is used for exposure of the small patterns or fine patterns which can not be resolved by the light-exposing method, or a fine pattern, and the exposure of the necessary irreducible minimum line width is conducted on a circuit. Also, the pattern can be changed easily and the manufacturing time of elements can be reduced by using the focussed ion beam exposing method. By combining the merit of said two exposing methods, the pattern can be changed easily, productivity is not lowered, and the integrated circuit containing fine patterns can be obtained.
JP62163758A 1987-06-29 1987-06-29 Manufacture of integrated circuit Granted JPS647520A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62163758A JPS647520A (en) 1987-06-29 1987-06-29 Manufacture of integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62163758A JPS647520A (en) 1987-06-29 1987-06-29 Manufacture of integrated circuit

Publications (2)

Publication Number Publication Date
JPS647520A true JPS647520A (en) 1989-01-11
JPH0548927B2 JPH0548927B2 (en) 1993-07-22

Family

ID=15780143

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62163758A Granted JPS647520A (en) 1987-06-29 1987-06-29 Manufacture of integrated circuit

Country Status (1)

Country Link
JP (1) JPS647520A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5892223A (en) * 1981-11-27 1983-06-01 Matsushita Electronics Corp Resist pattern formation

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5892223A (en) * 1981-11-27 1983-06-01 Matsushita Electronics Corp Resist pattern formation

Also Published As

Publication number Publication date
JPH0548927B2 (en) 1993-07-22

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