JPS6473642A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6473642A JPS6473642A JP23012787A JP23012787A JPS6473642A JP S6473642 A JPS6473642 A JP S6473642A JP 23012787 A JP23012787 A JP 23012787A JP 23012787 A JP23012787 A JP 23012787A JP S6473642 A JPS6473642 A JP S6473642A
- Authority
- JP
- Japan
- Prior art keywords
- wiring layer
- deposited
- metal wiring
- bias
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
PURPOSE:To eliminate troubles, such as displacement of mask alignment, impossibility of mask alignment by depositing a lower metal wiring layer under good condition of step coverage on a semiconductor substrate formed with a contact window, and further depositing an upper metal wiring layer of the same composition as that of the upper layer under the condition of eliminating the surface roughness thereon. CONSTITUTION:An interlayer insulating film 2, such as an SiO2 film is deposited by a CVD method in length of 1.0mum, and a contact window 3 is formed by photolithographic and etching steps on the film 2. Then, a lower metal wiring layer 4 is deposited 0.6mum by a bias sputtering method. Further, an upper metal wiring layer 5 is deposited 0.4mum on the layer 4 by a normal sputtering method without bias. In this case, since the surface of the wiring layer is covered with a layer deposited by the normal sputtering method without bias on the whole surface, its surface roughness can be considerably alleviated.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23012787A JPS6473642A (en) | 1987-09-14 | 1987-09-14 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23012787A JPS6473642A (en) | 1987-09-14 | 1987-09-14 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6473642A true JPS6473642A (en) | 1989-03-17 |
Family
ID=16902995
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23012787A Pending JPS6473642A (en) | 1987-09-14 | 1987-09-14 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6473642A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102768335A (en) * | 2012-06-29 | 2012-11-07 | 福州瑞芯微电子有限公司 | Circuit and method for monitoring chip internal circuit signal |
-
1987
- 1987-09-14 JP JP23012787A patent/JPS6473642A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102768335A (en) * | 2012-06-29 | 2012-11-07 | 福州瑞芯微电子有限公司 | Circuit and method for monitoring chip internal circuit signal |
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