JPS5795647A - Integrated circuit device and its manufacture - Google Patents

Integrated circuit device and its manufacture

Info

Publication number
JPS5795647A
JPS5795647A JP17225680A JP17225680A JPS5795647A JP S5795647 A JPS5795647 A JP S5795647A JP 17225680 A JP17225680 A JP 17225680A JP 17225680 A JP17225680 A JP 17225680A JP S5795647 A JPS5795647 A JP S5795647A
Authority
JP
Japan
Prior art keywords
film
flattened
wiring layer
wiring
shaped
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17225680A
Other languages
Japanese (ja)
Inventor
Tomoyuki Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Faurecia Clarion Electronics Co Ltd
Original Assignee
Clarion Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Clarion Co Ltd filed Critical Clarion Co Ltd
Priority to JP17225680A priority Critical patent/JPS5795647A/en
Publication of JPS5795647A publication Critical patent/JPS5795647A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To prevent the breaking of a stage in multilayer wiring structure, and to enable fining by a method wherein an insulating film is coated and formed onto a substrate to which the first wiring layer with difference in stages is formed, and flattened, and the second wiring layer is shaped to the upper section. CONSTITUTION:The first Al wiring layers 4 are formed to the Si substrate 1, to which a desired circuit element 2 consisting of a diffusion layer, etc. is shaped, through a SiO2 film 3, the CVDSiO2 film 5 is coated, and a resist film 9 is applied rotatively so that the surface is flattened. The whole surface of the resist film 9 is exposed, and developed so that resist films 9A remain in the thick concave sections of the film 9. An exposed section of the SiO2 film 5 is etched and flattened, a contact hole 7 is formed to the film 5, and the second wiring layer such as an Al wiring layer 6 is shaped. Accordingly, disconnection due to the difference in stages of the upper layer wiring layers can be prevented, and yield and reliability can be improved.
JP17225680A 1980-12-05 1980-12-05 Integrated circuit device and its manufacture Pending JPS5795647A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17225680A JPS5795647A (en) 1980-12-05 1980-12-05 Integrated circuit device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17225680A JPS5795647A (en) 1980-12-05 1980-12-05 Integrated circuit device and its manufacture

Publications (1)

Publication Number Publication Date
JPS5795647A true JPS5795647A (en) 1982-06-14

Family

ID=15938514

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17225680A Pending JPS5795647A (en) 1980-12-05 1980-12-05 Integrated circuit device and its manufacture

Country Status (1)

Country Link
JP (1) JPS5795647A (en)

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