JPS6447075A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6447075A JPS6447075A JP62203522A JP20352287A JPS6447075A JP S6447075 A JPS6447075 A JP S6447075A JP 62203522 A JP62203522 A JP 62203522A JP 20352287 A JP20352287 A JP 20352287A JP S6447075 A JPS6447075 A JP S6447075A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- pillar
- region
- film
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE:To avoid increase of contact resistance and nonconduction due to insufficient burying of wiring metal, by applying an intermediate insulating film onto a substrate except pillars which are formed of a part of the substrate and by electrically connecting the wiring and the semiconductor substrate through the pillars. CONSTITUTION:A silicon substrate 21 is separated into a field region and an active region by a field oxide film 22 which is selectively formed onto the substrate 21. In the active region, a gate electrode 23 and a gate oxide film 24 are lamination-formed onto the substrate 21 and a source-drain region 25 is formed within the substrate 21. A pillar 26 is prepared by a part of the substrate 21 so that is projects on the region 25. The surface of the substrate 21 excepting the pillar 26 is entirely covered with intermediate insulating film 27 on a level with the top of pillar 26. A wiring 28 is electrically connected with the source drain region 25 through the pillar 26. If the top of pillar 12 is lower than that of the film 27, a contact hole can be shortened by the length differential between the two. Therefore, if the length of pillar 12 is more than about half the thickness of film 27, burying efficiency can be improved.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62203522A JPS6447075A (en) | 1987-08-18 | 1987-08-18 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62203522A JPS6447075A (en) | 1987-08-18 | 1987-08-18 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6447075A true JPS6447075A (en) | 1989-02-21 |
Family
ID=16475542
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62203522A Pending JPS6447075A (en) | 1987-08-18 | 1987-08-18 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6447075A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015159337A (en) * | 2015-06-04 | 2015-09-03 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. | Semiconductor device manufacturing method and semiconductor device |
-
1987
- 1987-08-18 JP JP62203522A patent/JPS6447075A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015159337A (en) * | 2015-06-04 | 2015-09-03 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. | Semiconductor device manufacturing method and semiconductor device |
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