JPS6441053A - Programmable/relocatable i/o decoder - Google Patents

Programmable/relocatable i/o decoder

Info

Publication number
JPS6441053A
JPS6441053A JP19637187A JP19637187A JPS6441053A JP S6441053 A JPS6441053 A JP S6441053A JP 19637187 A JP19637187 A JP 19637187A JP 19637187 A JP19637187 A JP 19637187A JP S6441053 A JPS6441053 A JP S6441053A
Authority
JP
Japan
Prior art keywords
address
contents
decoder
processor
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19637187A
Other languages
Japanese (ja)
Inventor
Shinjirou Nagaoka
Akira Kawasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP19637187A priority Critical patent/JPS6441053A/en
Publication of JPS6441053A publication Critical patent/JPS6441053A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To freely change the I/O address of an I/O when viewed from a processor by adding the contents of a specific address in a memory space with the contents of the I/O address received from the processor and giving the result of this addition to an I/O decoder. CONSTITUTION:A relocation register 1 holds the contents of a data bus DB by the signal obtained by decoding an address received from a memory address decoding line L. Then the contents of the register 1 are added with an I/O address Ad received from a processor by an adder 2. The result of this addition is given to an I/O decoder 3 and an I/O selection signal SEL is produced. The processor changes the contents of the register 1 positioned at an address in a memory space. Thus it is possible to obtain a relocatable I/O connected to the decoder 3 by a program.
JP19637187A 1987-08-07 1987-08-07 Programmable/relocatable i/o decoder Pending JPS6441053A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19637187A JPS6441053A (en) 1987-08-07 1987-08-07 Programmable/relocatable i/o decoder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19637187A JPS6441053A (en) 1987-08-07 1987-08-07 Programmable/relocatable i/o decoder

Publications (1)

Publication Number Publication Date
JPS6441053A true JPS6441053A (en) 1989-02-13

Family

ID=16356747

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19637187A Pending JPS6441053A (en) 1987-08-07 1987-08-07 Programmable/relocatable i/o decoder

Country Status (1)

Country Link
JP (1) JPS6441053A (en)

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