JPS644079A - Manufacture of junction type fet - Google Patents

Manufacture of junction type fet

Info

Publication number
JPS644079A
JPS644079A JP15907487A JP15907487A JPS644079A JP S644079 A JPS644079 A JP S644079A JP 15907487 A JP15907487 A JP 15907487A JP 15907487 A JP15907487 A JP 15907487A JP S644079 A JPS644079 A JP S644079A
Authority
JP
Japan
Prior art keywords
gate electrode
diffusion region
layer
type fet
manufacture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15907487A
Other languages
Japanese (ja)
Inventor
Takeshi Yagihara
Hirofumi Matsuda
Shinji Kobayashi
Akira Miura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yokogawa Electric Corp
Original Assignee
Yokogawa Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yokogawa Electric Corp filed Critical Yokogawa Electric Corp
Priority to JP15907487A priority Critical patent/JPS644079A/en
Publication of JPS644079A publication Critical patent/JPS644079A/en
Pending legal-status Critical Current

Links

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To make position alignment between a gate electrode and a p<+> diffusion region needless to upgrade integrity, by diffusing p-type impurities from a gate electrode to a semiconductor substrate just under the gate electrode. CONSTITUTION:After a gate electrode 7 is selectively formed on a surface of an (n) layer, ramp annealing is performed to diffuse p-type impurities from the gate electrode 7 to the (n) layer 2 just under the gate electrode 7 so that a p<+> diffusion region 8 is formed. A pn junction is thus formed between the (n) layer 2 and the p<+> diffusion region 8. The p<+> diffusion region 8 of a junction type FET composed in this way is formed with the gate electrode 7 as a diffusion source, and so fine processing can be realized sufficiently according to precision in the processing of the gate electrode 7, and also integrity can be upgraded.
JP15907487A 1987-06-26 1987-06-26 Manufacture of junction type fet Pending JPS644079A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15907487A JPS644079A (en) 1987-06-26 1987-06-26 Manufacture of junction type fet

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15907487A JPS644079A (en) 1987-06-26 1987-06-26 Manufacture of junction type fet

Publications (1)

Publication Number Publication Date
JPS644079A true JPS644079A (en) 1989-01-09

Family

ID=15685651

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15907487A Pending JPS644079A (en) 1987-06-26 1987-06-26 Manufacture of junction type fet

Country Status (1)

Country Link
JP (1) JPS644079A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60220975A (en) * 1984-04-18 1985-11-05 Toshiba Corp Gaas field-effect transistor and manufacture thereof

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60220975A (en) * 1984-04-18 1985-11-05 Toshiba Corp Gaas field-effect transistor and manufacture thereof

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