JPS6432722A - Parallel/serial converting circuit - Google Patents
Parallel/serial converting circuitInfo
- Publication number
- JPS6432722A JPS6432722A JP18751387A JP18751387A JPS6432722A JP S6432722 A JPS6432722 A JP S6432722A JP 18751387 A JP18751387 A JP 18751387A JP 18751387 A JP18751387 A JP 18751387A JP S6432722 A JPS6432722 A JP S6432722A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- counter
- output
- serial
- bits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Communication Control (AREA)
Abstract
PURPOSE:To prevent a misoperation due to a lacing by switching the output sequence of a multiplexer output by means of the output of a counter for generating the load timing of parallel data and a shifting control signal. CONSTITUTION:By a clearing signal, parallel registers 1 and 2 and a three bits up counter 6 are reset, and by the leading edge of a clock signal 14, the three bits up counter 6 starts an action. The output sequence of a serial signal 18 is determined by outputs 60-62 of EOR circuits 8-10 to input the outputs 50-52 of the three bits up counter and a shifting direction designating signal 16. A flip flop 4 relatches the serial output 18 by a phase-shifted clock signal 15 and outputs it as a serial output 19 in order to prevent a bazard signal from being serial-outputted by the changeable timing of a counter value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18751387A JPS6432722A (en) | 1987-07-29 | 1987-07-29 | Parallel/serial converting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18751387A JPS6432722A (en) | 1987-07-29 | 1987-07-29 | Parallel/serial converting circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6432722A true JPS6432722A (en) | 1989-02-02 |
Family
ID=16207385
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18751387A Pending JPS6432722A (en) | 1987-07-29 | 1987-07-29 | Parallel/serial converting circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6432722A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03141473A (en) * | 1989-10-27 | 1991-06-17 | Hitachi Ltd | Input/output circuit for picture data rotated at optional angle |
| JP2010141441A (en) * | 2008-12-09 | 2010-06-24 | Fujitsu Ltd | Parallel-serial converter and data reception system |
| US8031233B2 (en) | 2002-02-12 | 2011-10-04 | Sony Corporation | Solid-state image pickup device and method with time division video signal outputs |
-
1987
- 1987-07-29 JP JP18751387A patent/JPS6432722A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03141473A (en) * | 1989-10-27 | 1991-06-17 | Hitachi Ltd | Input/output circuit for picture data rotated at optional angle |
| US8031233B2 (en) | 2002-02-12 | 2011-10-04 | Sony Corporation | Solid-state image pickup device and method with time division video signal outputs |
| JP2010141441A (en) * | 2008-12-09 | 2010-06-24 | Fujitsu Ltd | Parallel-serial converter and data reception system |
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