JPS6428953A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6428953A
JPS6428953A JP18602987A JP18602987A JPS6428953A JP S6428953 A JPS6428953 A JP S6428953A JP 18602987 A JP18602987 A JP 18602987A JP 18602987 A JP18602987 A JP 18602987A JP S6428953 A JPS6428953 A JP S6428953A
Authority
JP
Japan
Prior art keywords
chip
insulation layer
contact
eqr electrode
conventionally
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18602987A
Other languages
Japanese (ja)
Inventor
Takeshi Nobe
Masahiko Suzumura
Shigeo Akiyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP18602987A priority Critical patent/JPS6428953A/en
Publication of JPS6428953A publication Critical patent/JPS6428953A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To make this device satisfiable with its chip area smaller than conventionally, by disposing an EQR electrode circularly on a peripheral part of an insulation layer on a chip surface so that it is in direct contact with a semiconductor substrate under the insulation layer and next forming contact parts locally. CONSTITUTION:An EQR electrode 5 is circularly disposed on a peripheral part of an insulation layer 4 on a chip T's surface where an FET is formed, and it is in contact with only four corners of the chip T. Namely the EQR electrode 5 is in direct contact with a semiconductor substrate 1 through holes 4a formed in the insulation layer 4 on the corners of the quadrangular chip T. The EQR electrode 5 is formed only on the insulation layer 4 at positions of sides of the chip T, but it does not contact with the semiconductor substrate 1 there. The EQR electrode 5 can be formed much larger in width in degree of no contact than conventionally at the positions of the sides of the chip T. Accordingly this device is made satisfiable with a small chip area without a large chip area required as conventionally.
JP18602987A 1987-07-24 1987-07-24 Semiconductor device Pending JPS6428953A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18602987A JPS6428953A (en) 1987-07-24 1987-07-24 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18602987A JPS6428953A (en) 1987-07-24 1987-07-24 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6428953A true JPS6428953A (en) 1989-01-31

Family

ID=16181149

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18602987A Pending JPS6428953A (en) 1987-07-24 1987-07-24 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6428953A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0438065U (en) * 1990-07-27 1992-03-31

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0438065U (en) * 1990-07-27 1992-03-31

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