JPS6423531A - Formation of die alignment mark - Google Patents

Formation of die alignment mark

Info

Publication number
JPS6423531A
JPS6423531A JP62179051A JP17905187A JPS6423531A JP S6423531 A JPS6423531 A JP S6423531A JP 62179051 A JP62179051 A JP 62179051A JP 17905187 A JP17905187 A JP 17905187A JP S6423531 A JPS6423531 A JP S6423531A
Authority
JP
Japan
Prior art keywords
alignment mark
intermediate layer
resist
die alignment
deteriorating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62179051A
Other languages
Japanese (ja)
Inventor
Norihiko Samoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62179051A priority Critical patent/JPS6423531A/en
Publication of JPS6423531A publication Critical patent/JPS6423531A/en
Pending legal-status Critical Current

Links

Landscapes

  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

PURPOSE:To prevent the detection accuracy during a detection operation of a mask position from deteriorating by a method wherein an intermediate layer which does not react with a semiconductor substrate and a die alignment mark is installed and a metal to be used as the alignment mark is formed on a recessed part formed on this intermediate layer so that the surface and an edge of the alignment mark are not roughened due to a heat treatment operation. CONSTITUTION:An intermediate layer 22 composed of SiO2 is grown on a GaAs semiconductor substrate 21; a first resist 23 is coated; a region to form die alignment mark is exposed and developed, after that, the intermediate layer 22 in an unnecessary part is removed by an etching operation. Then, the first resist 23 is removed by an organic cleaning operation; after that, a second resist 24 is coated; a die alignment mark pattern is formed on the intermediate layer 22 by an optical exposure operation; a development operation is executed. Furthermore, a position to form the alignment mark on the intermediate layer 22 is removed slightly by the etching operation; a recessed part 27 is formed. Then, metals 25 and 26 are evaporated. The second resist 24 and the metal 25 in an unnecessary part are removed by a lift-off method by the organic cleaning operation. By this setup, this can be utilized as the alignment mark whose surface is smooth and which has a uniform edge; after a heat treatment operation it is possible to prevent the position detection accuracy from deteriorating.
JP62179051A 1987-07-20 1987-07-20 Formation of die alignment mark Pending JPS6423531A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62179051A JPS6423531A (en) 1987-07-20 1987-07-20 Formation of die alignment mark

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62179051A JPS6423531A (en) 1987-07-20 1987-07-20 Formation of die alignment mark

Publications (1)

Publication Number Publication Date
JPS6423531A true JPS6423531A (en) 1989-01-26

Family

ID=16059265

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62179051A Pending JPS6423531A (en) 1987-07-20 1987-07-20 Formation of die alignment mark

Country Status (1)

Country Link
JP (1) JPS6423531A (en)

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