JPS6419777A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To decrease the source resistance with the gate electrode sheet resistance kept high and thereby to enhance its controllability by a method wherein a gate electrode built on a GaAs layer serves as a mask for the selective etching away of the GaAs layer and the resultant GaAs-free region is filled with a higher-concentration GaAs layer selectively formed. CONSTITUTION:By applying the MBE method, an undoped GaAs layer 2 is formed on a semi-insulating GaAs substrate 1, and then an Si-doped n-AlGaAs layer 3 and an n-GaAs layer 4 are deposited in lamination. Next, on the n-GaAs layer 4, a WSi-made heat resistant gate electrode 5 is built, which serves as a mask in a selective dry etching process, using CCl2F2+Ne gas, accomplished against GaAs/AlGaAs. As the result, the n-GaAs layer 4, except a part immediately under the gate electrode 5, is etched away. A process follows wherein an n<+>-GaAs layer 9 is selectively formed, by the AOCVD method using AsH3 and TMG, on the now-exposed n-AlGaAs layer 3. Finally, on the n<+>-GaAs layer 9, a source electrode 6 and a drain electrode 7 are formed in ohmic contact with the n<+>-GaAs layer 9, which completes a HEMT of this design.