JPS6466973A - Preparation of field effect transistor - Google Patents

Preparation of field effect transistor

Info

Publication number
JPS6466973A
JPS6466973A JP22465887A JP22465887A JPS6466973A JP S6466973 A JPS6466973 A JP S6466973A JP 22465887 A JP22465887 A JP 22465887A JP 22465887 A JP22465887 A JP 22465887A JP S6466973 A JPS6466973 A JP S6466973A
Authority
JP
Japan
Prior art keywords
layer
etching
gaas layer
electrode
selectively
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22465887A
Other languages
Japanese (ja)
Inventor
Yasutoshi Tsukada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP22465887A priority Critical patent/JPS6466973A/en
Publication of JPS6466973A publication Critical patent/JPS6466973A/en
Pending legal-status Critical Current

Links

Landscapes

  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To make it possible to manufacture a field effect transistor having large mutual conductance and capable of operating at high speed with good repeatability, by selectively growing an N-type semiconductor layer by an MOCVD method using an insulating side wall and a gate electrode as a mask and then etching it such that it becomes partially thin. CONSTITUTION:An undoped GaAs layer 3, an N<+> AlGaAs layer 2 and an undoped GaAs layer 1 are sequentially superposed on a semi-insulating GaAs substrate 4 and a gate electrode 5 is formed to form insulating side walls 6a and 6b comprising SiO2. An N<+> GaAs layer 7 is selectively grown by an MOCVD method using AsH3 and trimethylgalium and thinned by selectively etching the layer 7. Finally, an ohmic electrode (Au Ge) is provided on the thinned part to form a source electrode 8 and a drain electrode 9. Since the N<+> GaAs layer can be formed thickly, sheet resistance is decreased and since the part right beneath the source and drain electrodes is thin because of the etching, contact resistance can be reduced.
JP22465887A 1987-09-07 1987-09-07 Preparation of field effect transistor Pending JPS6466973A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22465887A JPS6466973A (en) 1987-09-07 1987-09-07 Preparation of field effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22465887A JPS6466973A (en) 1987-09-07 1987-09-07 Preparation of field effect transistor

Publications (1)

Publication Number Publication Date
JPS6466973A true JPS6466973A (en) 1989-03-13

Family

ID=16817176

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22465887A Pending JPS6466973A (en) 1987-09-07 1987-09-07 Preparation of field effect transistor

Country Status (1)

Country Link
JP (1) JPS6466973A (en)

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