JP3082401B2 - Selective etchant and method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for producing a selected etchant and a semiconductor device.

[0002]

2. Description of the Related Art An n-type AlG is formed on a non-doped GaAs layer.
In the heterojunction structure in which the aAs layer is formed, a high-mobility two-dimensional electron gas is formed on the GaAs side of the heterojunction interface.
A heterojunction field effect transistor called T) was invented. In order to further improve the characteristics of the HEMT, many studies have been made in terms of materials and structures. In terms of material, In _0.53 lattice-matched to InP instead of GaAs
Ga _0.47 As was used, and InAl was used instead of AlGaAs.
The one using As is an AlGaAs / GaAs HEM.
It shows higher electron mobility, higher electron saturation velocity, and higher two-dimensional electron gas concentration than T, and is very promising as an ultra-high-speed, low-noise device. Further, a structure has been proposed in which an InGaAs contact layer having a small band gap is formed on the InAlAs layer in order to facilitate ohmic contact between a source electrode and a drain electrode in a process of forming an element. Regarding device fabrication, when fabricating a compound semiconductor integrated circuit, it is necessary to electrically isolate each element constituting the integrated circuit.
Isolation between elements of an s-based HEMT is generally performed by mesa etching. In forming the electrodes,
After the formation of the source / drain electrodes, the InGaAs contact layer in the region where the Schottky gate electrode is to be formed is removed, and then a gate metal is formed on InAlAs.

[0003]

However, as shown in FIG. 1, when element isolation is performed by mesa etching, the gate metal 3 comes into contact with the mesa side wall 5, so that InGaAs having a low Schottky barrier height is used.
Since a leak path is generated between the s-channel layer 4 and the gate electrode 3, there is a problem that the gate breakdown voltage is deteriorated when the FET is manufactured, which causes deterioration of individual device characteristics. In addition, I in the region where the Schottky gate electrode is formed
In the step of removing the nGaAs contact layer, a conventional phosphoric acid-based etching solution is used to form InAlA for forming a gate electrode.
Since it was difficult to control the etching depth of the s layer accurately, there was a problem that it was difficult to control the threshold value of the FET accurately. To solve these problems,
By selectively etching the InGaAs layer,
A method of spatially separating the gate metal 3 and the InGaAs channel layer 4 and a method of forming a gate electrode by using an InAlAs layer forming a gate electrode as an etching stopper layer can be considered. There was no etchant that could be etched.

The present invention solves such a conventional problem and can selectively etch the InGaAs channel layer and the InGaAs contact layer of the mesa side wall, so that the InGaAs channel layer and the gate metal can be electrically separated. Further, it is an etchant that can provide an extremely excellent compound semiconductor device having excellent FET threshold controllability.

[0005]

In order to achieve this object, the present invention provides tartaric acid (C4H6O6), aqueous hydrogen peroxide and
Etchant containing a mixture containing hydrogen and ammonia
And a compound including an InGaAs layer and an InAlAs layer.
In the semiconductor layer, the InGaAs layer is selectively etched.
It is used as a selective etching liquid for a semiconductor to be etched. Like
Alternatively, the concentration of tartaric acid contained in the mixture is 10
0 μmol / cc or less. In addition, an InGaAs layer and
A method for manufacturing a semiconductor device including an InAlAs layer, comprising:
Using the etching solution, the InGaAs layer is selectively formed.
A method of manufacturing a semiconductor device including an etching step.
You.

This method comprises the steps of dissolving tartaric acid crystals in water to prepare a tartaric acid aqueous solution, and mixing ammonia water, hydrogen peroxide solution and the tartaric acid aqueous solution, wherein the tartaric acid / ammonia / hydrogen peroxide mixture Use a tartaric acid having a concentration of 100 μmol / cc or less.

[0007]

In InGaAs and InAlAs, in the mixed solution of tartaric acid, ammonia water and hydrogen peroxide,
It is not clear whether aAs is selectively etched. However, as will be described in more detail with reference to examples, when the content of tartaric acid is increased while the content of ammonia is kept constant, the etching rate also tends to increase, whereas the selectivity is almost the same. From showing a constant value,
Whether the addition of ammonia causes any chemical change to prevent etching on the surface of InAlAs,
Alternatively, it is presumed that ammonia acts as a catalyst to promote the etching of InGaAs. According to the present invention, by selectively etching the InGaAs channel layer of the mesa sidewall, the InGaAs channel layer and the gate electrode can be completely completely electrically separated.
Since the nAlAs barrier layer can be used as an etching stopper layer, the controllability of the threshold value of the FET is good and a uniform element can be obtained.
This greatly contributes to integration.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As a first embodiment of the present invention, a method for producing an InGaAs selective etching solution comprising a mixed solution of tartaric acid aqueous solution (C ₄ H ₆ O ₆ ), hydrogen peroxide solution and aqueous ammonia will be described. First, accurately measure 1 liter of ultrapure water with a measuring cylinder and transfer it to a beaker. Tartaric acid crystals (C
200 g of ₄ H ₆ O ₆ ) is accurately measured with an electronic balance, added to ultrapure water in a beaker, and stirred well to prepare a tartaric acid aqueous solution. Next, ammonia water 1 with an ammonia content of 29%
Hydrogen peroxide water 200c with cc and hydrogen peroxide content of 30%
A mixed solution of c is prepared. Finally, several cc of the aqueous solution of tartaric acid is mixed with a mixed solution of aqueous ammonia and hydrogen peroxide and stirred well to complete a selective etching solution using a mixed liquid of tartaric acid, ammonia and hydrogen peroxide. Incidentally, if the tartaric acid aqueous solution and the ammonia water are mixed at first, a compound of tartaric acid and ammonia is precipitated, and the precipitate is not dissolved even by adding hydrogen peroxide solution, and a desired selective etching solution is obtained. I can't do things.

Next, as a second embodiment of the present invention, an example of experimental data showing the effect of selective etching of InGaAs and InAlAs using a mixed solution of tartaric acid, ammonia and hydrogen peroxide prepared in the first embodiment. Is shown. In order to show the selective etching amount of InGaAs, which is the object of the present invention, InGaAs lattice-matched with InP is formed on an InP substrate.
And InAlAs were grown by about 5000 ° each by MBE, half of each sample was covered with a resist, etched in a selective etching solution for 10 minutes, and the step was measured with a step film pressure gauge. The result is shown in FIG. As is clear from Table 1, when the amount of tartaric acid is increased while the amount of ammonia is kept constant, the etching rate also tends to increase.
The selectivity shows a substantially constant value of 5 to 7, the amount of etching depends on the concentration of tartaric acid, and it is considered that ammonia mainly contributes to the selectivity. The effect was confirmed. Although not shown here, if the concentration of tartaric acid is too high (100 μmol / c
c or more) Although the etching rate of InGaAs also increases,
Since the etching rate of InAlAs also increases, it is not suitable as a selective etching solution.

Next, as a third embodiment of the present invention, tartaric acid
InGaAs using a mixture of ammonia and hydrogen peroxide
An s / InAlAs HEMT was prototyped, the source-gate current-voltage characteristics (Vgs-Igs) were measured, and the effect of selective etching was examined. FIG. 3 is a cross-sectional structural view of a prototype HEMT, wherein 6 is a semi-insulating InP substrate, 7 is a non-doped InAlAs buffer layer 3000 #, 8 is a non-doped InGaAs channel layer 300 #, 9 is a non-doped InAlAs spacer layer 30 #, and 10 is a Si impurity. 5 × 10 ¹⁸ cm ⁻³ doped n-type InAlAs carrier supply layers 100 #, 11 are non-doped InAlAs barrier layers 200 #, 12 are non-doped InGaAs contact layers 100 #, and grown by MBE.
In fabricating the FET, the isolation between the elements is H ₃ PO ₄ : H
After performing mesa etching of about 2000 ° using a phosphoric acid-based etching solution of ₂ O ₂ : H ₂ O = 3: 1: 50 (FIG. 4), an aqueous solution of tartaric acid of the present invention: aqueous ammonia: hydrogen peroxide = 2: 1. : 200 was selectively etched for 3 minutes using a mixed solution of Mesa side wall (FIG. 5). After that, the source electrode 1 of the FET
And Ge / Au / Ni / Ti / Au as the drain electrode 2
(FIG. 6), and a non-doped InGaAs cap layer at a gate portion where a Schottky electrode is formed using a mixture of tartaric acid aqueous solution: aqueous ammonia: hydrogen peroxide = 2: 1: 200 according to the present invention. 12 was selectively removed (FIG. 7), and a gate electrode 3 was formed using an electrode material of Ti / Pt / Au (FIG. 8). At this time, the gate electrode 3 and the non-doped I
An air gap exists between the nGaAs channel layers 8 and is spatially separated. FIG. 9 shows a prototype InGaAs.
4 is a graph showing a source-gate current-voltage characteristic (Vgs-Igs) of / InAlAs HEMT. In the sample not subjected to the selective etching, the gate metal comes into contact with the non-doped InGaAs channel layer of the mesa side wall, so that the rising voltage in the forward direction is low due to the low Schottky barrier height of InGaAs. Further I
Since a leak path is generated between the nGaAs channel and the gate, the reverse breakdown voltage is also poor. On the other hand, the sample subjected to the selective etching shows good Schottky characteristics because an air gap exists between the gate electrode 3 and the non-doped InGaAs channel layer 8 and is spatially separated. Although not shown here, the variation of the threshold value is extremely small, and the FET having a good threshold value controllability.
Could be produced. From the results of the above examples, the effectiveness of the compound semiconductor selective etching solution of the present invention was confirmed.

[0011]

As described above, the compound semiconductor selective etching solution of the present invention can be used to form InGaAs / InAlA.
The gate breakdown voltage is greatly improved by selectively etching the InGaAs channel layer of the s-based HEMT, and the InGaAs contact layer can be selectively removed by using the InAlAs barrier layer as an etching stopper layer, so that the FET with good threshold controllability. Not only can produce
This has the effect of improving the characteristics of the device itself and further enabling integration. In the embodiment of the present invention, the HEM is mainly used.
Although T has been described, the scope of the present invention is not limited to this, and electric devices such as HFET and HBT,
Needless to say, it is possible to support optical devices such as light receiving elements.

[Brief description of the drawings]

FIG. 1 is a perspective view of a conventional FET manufactured only by mesa etching.

FIG. 2 is a diagram showing experimental results of etching rates and selectivity of InGaAs and InAlAs with a mixed solution of tartaric acid, ammonia and hydrogen peroxide solution of the present invention.

FIG. 3 shows InGaAs / InAlAs according to an embodiment of the present invention.
HEMT structure diagram

FIG. 4 shows InGaAs / InAlAs according to an embodiment of the present invention.
HEMT first process sectional view

FIG. 5 shows InGaAs / InAlAs according to an embodiment of the present invention.
HEMT second process sectional view

FIG. 6 shows InGaAs / InAlAs according to an embodiment of the present invention.
HEMT Third Process Sectional View

FIG. 7 shows InGaAs / InAlAs according to an embodiment of the present invention.
HEMT fourth process sectional view

FIG. 8 shows InGaAs / InAlAs according to an embodiment of the present invention.
HEMT Fifth Process Sectional View

FIG. 9 shows InGaAs / InAlAs according to an embodiment of the present invention.
Source-gate current-voltage characteristic diagram of HEMT (Vgs
-Igs)

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 Source electrode 2 Drain electrode 3 Gate electrode 4 InGaAs channel layer 5 Mesa side wall 6 Semi-insulating InP substrate 7 Non-doped InAlAs buffer layer 8 Non-doped InGaAs channel layer 9 Non-doped InAlAs spacer layer 10 n-type InAlAs carrier supply layer 11 Non-doped InAlAs barrier layer 12 Non-doped InGaAs contact layer

────────────────────────────────────────────────── ─── Continuation of the front page (72) Akira Ryuji, Inventor 1006 Kazuma Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) References JP-A-3-219000 (JP, A) JP-A-63-63 6846 (JP, A) JP-A-1-157536 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21 / 306,21 / 308 H01L 21 / 338,29 / 812

Claims (5)

(57) [Claims] 1. An etching solution mainly containing a mixed solution containing tartaric acid (C ₄ H ₆ O ₆ ), hydrogen peroxide solution and ammonia, wherein said compound semiconductor layer includes an InGaAs layer and an InAlAs layer. A semiconductor selective etchant that selectively etches layers. Wherein the concentration of tartaric acid contained in the etching solution, 100 [mu] mol / cc or less, according to claim 1 selected etchant according. 3. A method for manufacturing a semiconductor device including an InGaAs layer and an InAlAs layer, the method including a step of selectively etching the InGaAs layer using the selective etching solution according to claim 1 . 4. A method of manufacturing a field-effect transistor including an InGaAs layer and an InAlAs layer and having the InGaAs in an active layer, wherein the field-effect transistor is separated into island regions by mesa etching. using a selective etchant of claim 1, wherein a step of selectively etching the InGaAs layer of the sidewall of the island regions, the method of manufacturing a semiconductor device according to claim 3, wherein. 5. The semiconductor device according to claim 1, further comprising an InAlAs barrier layer,
A method for manufacturing a field-effect transistor having an InGaAs contact layer on an nAlAs barrier layer, the method comprising:
2. The InGaAs barrier layer is used as an etching stopper layer by using the selective etching solution according to 1.
Selectively removing the contact layer;
4. The method of manufacturing a semiconductor device according to claim 3 , further comprising: forming a gate electrode on the As barrier layer.