JPS6419765A - Manufacture of semiconductor integrated circuit device - Google Patents
Manufacture of semiconductor integrated circuit deviceInfo
- Publication number
- JPS6419765A JPS6419765A JP17462187A JP17462187A JPS6419765A JP S6419765 A JPS6419765 A JP S6419765A JP 17462187 A JP17462187 A JP 17462187A JP 17462187 A JP17462187 A JP 17462187A JP S6419765 A JPS6419765 A JP S6419765A
- Authority
- JP
- Japan
- Prior art keywords
- sidewalls
- insulating film
- film
- high dimensional
- dimensional controllability
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Bipolar Transistors (AREA)
Abstract
PURPOSE:To form an emitter region and graft base regions in a manner of self- alignment and high dimensional controllability, by a method wherein sidewalls are formed on the side surfaces of a prescribed step pattern and an thermal oxidation is performed using this step pattern and these sidewalls as oxide masks to form an insulating film. CONSTITUTION:An insulating film (anti-oxidation film) 8 is, formed on the whole surface and after an insulating film 9 is formed, this film 9 is anisotropically etched and an insulating film 9 (a step pattern) of a prescribed form having side surfaces vertical to the surface of a p<+> semiconductor substrate 1 is formed. Then, an insulating film is formed on the whole surface and this insulating film is subjected to anisotropic etching to form sidewalls 11 consisting of an insulator. The width of these sidewalls 11 can be decided in a high dimensional controllability by selecting the thickness of the insulating film. Then, the insulating films 10 and 8 and an insulating film 6 are etched using the sidewalls 11, the film 9 and so on as masks to expose partially an epitaxial layer 3, insulating films are formed in order on the whole surface and an anisotropic etching is performed to form sidewalls 13 consisting of an insulator. As the width of these sidewalls 13 can be also decided in a manner of high dimensional controllability like that of the sidewalls 11, p<+> graft base regions 15 can be formed in a manner of high dimensional controllability.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17462187A JPS6419765A (en) | 1987-07-15 | 1987-07-15 | Manufacture of semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17462187A JPS6419765A (en) | 1987-07-15 | 1987-07-15 | Manufacture of semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6419765A true JPS6419765A (en) | 1989-01-23 |
Family
ID=15981794
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17462187A Pending JPS6419765A (en) | 1987-07-15 | 1987-07-15 | Manufacture of semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6419765A (en) |
-
1987
- 1987-07-15 JP JP17462187A patent/JPS6419765A/en active Pending
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