JPS6417445A - Standard cell - Google Patents
Standard cellInfo
- Publication number
- JPS6417445A JPS6417445A JP17322087A JP17322087A JPS6417445A JP S6417445 A JPS6417445 A JP S6417445A JP 17322087 A JP17322087 A JP 17322087A JP 17322087 A JP17322087 A JP 17322087A JP S6417445 A JPS6417445 A JP S6417445A
- Authority
- JP
- Japan
- Prior art keywords
- region
- wiring
- recessed
- central part
- cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000010354 integration Effects 0.000 abstract 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
PURPOSE:To realize high integration, by disposing a power source line and an earth line horizontally on a central part and forming a recessed/projected region on a series of cells to make a wiring region small. CONSTITUTION:A power source line 2 is disposed horizontally in a constant width on a central part of a cell by the use of a metallic wiring on a first layer. An earth line 4 is also disposed horizontally in a constant width on the central part of the cell by the use of the metallic wiring on the first layer. Input lines 6, 8 are disposed vertically by the use of polycrystalline silicon. Thereupon, gate electrodes of all MOSFETs existing in a standard cell are disposed vertically. A recessed/projected region is thus formed on a series of cells. When one portion of a wiring region is assigned to the recessed/projected region, the wiring region can be made smaller than conventionally. Hence, high integration can be realized.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62173220A JP2661916B2 (en) | 1987-07-10 | 1987-07-10 | Standard cell |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62173220A JP2661916B2 (en) | 1987-07-10 | 1987-07-10 | Standard cell |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP28489695A Division JP2596406B2 (en) | 1995-11-01 | 1995-11-01 | Semiconductor integrated circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6417445A true JPS6417445A (en) | 1989-01-20 |
JP2661916B2 JP2661916B2 (en) | 1997-10-08 |
Family
ID=15956359
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62173220A Expired - Lifetime JP2661916B2 (en) | 1987-07-10 | 1987-07-10 | Standard cell |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2661916B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0325951A (en) * | 1989-06-23 | 1991-02-04 | Nec Corp | Layout cell of semiconductor integrated circuit |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5759352A (en) * | 1980-09-26 | 1982-04-09 | Fujitsu Ltd | Manufacture of integrated circuit |
JPS5966146A (en) * | 1982-10-08 | 1984-04-14 | Toshiba Corp | Semiconductor integrated circuit device |
-
1987
- 1987-07-10 JP JP62173220A patent/JP2661916B2/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5759352A (en) * | 1980-09-26 | 1982-04-09 | Fujitsu Ltd | Manufacture of integrated circuit |
JPS5966146A (en) * | 1982-10-08 | 1984-04-14 | Toshiba Corp | Semiconductor integrated circuit device |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0325951A (en) * | 1989-06-23 | 1991-02-04 | Nec Corp | Layout cell of semiconductor integrated circuit |
Also Published As
Publication number | Publication date |
---|---|
JP2661916B2 (en) | 1997-10-08 |
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