JPS6481338A - Method of laying out semiconductor logic integrated circuit - Google Patents
Method of laying out semiconductor logic integrated circuitInfo
- Publication number
- JPS6481338A JPS6481338A JP62237334A JP23733487A JPS6481338A JP S6481338 A JPS6481338 A JP S6481338A JP 62237334 A JP62237334 A JP 62237334A JP 23733487 A JP23733487 A JP 23733487A JP S6481338 A JPS6481338 A JP S6481338A
- Authority
- JP
- Japan
- Prior art keywords
- block
- wiring
- terminals
- cells
- uppermost
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE:To eliminate wasteful bent of a wiring by wiring a region between lowermost and uppermost cell rows to be regarded as a wiring region at the time of wiring in a logic block, and wiring with the terminals of the cells disposed at the uppermost/lowermost cell rows to be regarded as the terminals of the upper/lower sides of the logic block at the time of wiring between the logic block and already designed block. CONSTITUTION:An imaginary boundary side is provided at a logic block. Then, terminals are set on the side of the block due to certain object function, and logic cells are disposed by considering connecting relations of the terminal and between the cells. Then, a schematic wiring route is determined in accordance with connecting requests of the terminal of the side of the block and between the disposed cells, and the terminals are actually wired therebetween on a region between the uppermost/lowermost cell rows in the block. The blocks are eventually wired therebetween. In this case, the terminals of upper/lower sides of the cells of the uppermost/lowermost cell rows of the block are recognized as the terminals of the upper/lower sides of the block, and wirings are performed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62237334A JPS6481338A (en) | 1987-09-24 | 1987-09-24 | Method of laying out semiconductor logic integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62237334A JPS6481338A (en) | 1987-09-24 | 1987-09-24 | Method of laying out semiconductor logic integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6481338A true JPS6481338A (en) | 1989-03-27 |
Family
ID=17013839
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62237334A Pending JPS6481338A (en) | 1987-09-24 | 1987-09-24 | Method of laying out semiconductor logic integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6481338A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0352253A (en) * | 1989-07-20 | 1991-03-06 | Matsushita Electric Ind Co Ltd | Methods for grouping and arranging cells |
| US5138311A (en) * | 1990-09-20 | 1992-08-11 | Motorola, Inc. | Communication system having adaptable message information formats |
| JPH0582726A (en) * | 1991-09-24 | 1993-04-02 | Nec Ic Microcomput Syst Ltd | Integrated circuit |
-
1987
- 1987-09-24 JP JP62237334A patent/JPS6481338A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0352253A (en) * | 1989-07-20 | 1991-03-06 | Matsushita Electric Ind Co Ltd | Methods for grouping and arranging cells |
| US5138311A (en) * | 1990-09-20 | 1992-08-11 | Motorola, Inc. | Communication system having adaptable message information formats |
| JPH0582726A (en) * | 1991-09-24 | 1993-04-02 | Nec Ic Microcomput Syst Ltd | Integrated circuit |
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