JPS641198A - Semiconductor memory - Google Patents

Semiconductor memory

Info

Publication number
JPS641198A
JPS641198A JP62155838A JP15583887A JPS641198A JP S641198 A JPS641198 A JP S641198A JP 62155838 A JP62155838 A JP 62155838A JP 15583887 A JP15583887 A JP 15583887A JP S641198 A JPS641198 A JP S641198A
Authority
JP
Japan
Prior art keywords
data
bit
test
time
function
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62155838A
Other languages
Japanese (ja)
Other versions
JPH011198A (en
Inventor
Seiji Yamaguchi
Masaru Nagayasu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP62-155838A priority Critical patent/JPH011198A/en
Priority claimed from JP62-155838A external-priority patent/JPH011198A/en
Publication of JPS641198A publication Critical patent/JPS641198A/en
Publication of JPH011198A publication Critical patent/JPH011198A/en
Pending legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)

Abstract

PURPOSE: To shorten the time of a functional test of a memory system by reading the inverted data of 1-bit or 2-bit stored data at each time as a test function in reading operation.
CONSTITUTION: When stored data are read, the inverted data of 1-bit or 2-bit stored data are read out at each time as the function test. Namely, erroneous data can be generated when reading is performed through an external terminal without rewriting write data. Further, which cycle and which bit data is wrong in are easily recognized by predetermining the algorithm of the generation of an error generated through an error generation terminal, and an error correcting function is easily tested in the memory system. Consequently, the test time of the function test of the memory system can be shortened.
COPYRIGHT: (C)1989,JPO&Japio
JP62-155838A 1987-06-23 semiconductor memory Pending JPH011198A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62-155838A JPH011198A (en) 1987-06-23 semiconductor memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62-155838A JPH011198A (en) 1987-06-23 semiconductor memory

Publications (2)

Publication Number Publication Date
JPS641198A true JPS641198A (en) 1989-01-05
JPH011198A JPH011198A (en) 1989-01-05

Family

ID=

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012008620A (en) * 2010-06-22 2012-01-12 Fujitsu Ltd Error correction test method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012008620A (en) * 2010-06-22 2012-01-12 Fujitsu Ltd Error correction test method

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