JPH011198A - semiconductor memory - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION This invention relates to a test function for semiconductor memories.

BACKGROUND OF THE INVENTION FIG. 2 shows a block configuration of a conventional semiconductor memory. To briefly explain FIG. 2, 2 is a row address buffer, 4 is a row decoder, 6 is a memory cell array, 8 is a sense amplifier and write circuit, 1o is a column decoder, 12 is a column address buffer, and 14 is an input data control circuit. , 16 is an input data buffer, 18 is an output data buffer, 2o
is an operation control circuit, 22 is a row address terminal, 24 is a column address terminal, 26 is an input/output data terminal (Ilo), 28 is a write operation control terminal (WE), 30 is a chip selection terminal (CS), and 32 is an output control terminal (OE).

All general-purpose semiconductor memories in which input data terminals and output data terminals are shared have the configuration shown in FIG. 2. The outline of the operation shown in FIG. 2 is as follows depending on the state of the control signal of the operation control circuit 2o.

C8WE OE Ilo XXZ HHX in HL Hout LLZ However, X is an undefined state, Z is a high impedance state, i
n is a data input state, and out is a data output state.

The storage capacity of such general-purpose semiconductor memories has recently been rapidly increased. Furthermore, although the memory system is configured using a large number of general-purpose semiconductor memories, an error correction code is used to realize a highly reliable memory system.

In a memory system using an error correction code, it is necessary to check whether the memory system is correctly correcting errors. This requires extra hardware to perform a functional test of the memory system. This additional hardware complicates the memory system design and reduces packaging density. moreover,
The test time required for functional tests will also decrease as memory capacity increases.
It gets thicker.

However, a conventional general-purpose semiconductor memory as shown in FIG. 2 does not have an on-chip test function to perform when such a memory system is configured.

Problems to be Solved by the Invention As described above, when a memory system is constructed using conventional semiconductor memories and an error correction function is introduced, a great deal of effort is required to test the error correction function. Furthermore, as the storage capacity of the memory system increases, the test time increases.

The present invention aims to shorten the test time for functional testing of a memory system by incorporating a function for testing the error correction function of a memory system using a semiconductor memory on-chip in the semiconductor memory.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides a plurality of input/output data terminals and one bit per readout for data stored as a test function during readout operation. Alternatively, the semiconductor memory is characterized by comprising means for reading out inverted data of 2 bits of stored data, and control means for controlling the means using a control terminal.

Function: Since the present invention can automatically generate error data using the control terminal with the above-described configuration, it is possible to easily test the error correction function in the memory system.

Embodiment FIG. 1 is a concrete block diagram of the present invention. 1st
In the figure, 2 is a row address buffer, 4 is a row decoder, 6 is a memory cell array, 8 is a sense amplifier and write circuit, 10 is a column decoder, 12 is a column address buffer, 14 is an input data control circuit, and 16 is an input data buffer. , 18 is an output data buffer, 2o is an operation control circuit, 22 is a row address terminal, 24 is a column address terminal, 26
is the Ilo data terminal, and 28 is the write operation control terminal (
WE), 30 is a chip selection terminal (C8), 32 is an output control terminal (OE), and 34 is an error data generation circuit.

36 and 38 are error data generation terminals (EGl, EG2).

The operation control circuit 2o operates as follows depending on the state of the input control signal.

C3WEOE EG1EG2 I10 XXXXZ HHX X
n is the data input state, out is the data output state, 1-bit error generation is a state in which erroneous data is output to 1 bit of multiple Ilo data terminals, and 2-bit error generation is a state in which erroneous data is output to 1 bit of multiple Ilo data terminals. A state in which erroneous data is output to 2 bits, 1/2 bit error generation is multiple! This is a state in which erroneous data is output to one bit of the four data terminals, or erroneous data is output to two bits of the four data terminals.

Multiple 1-bit errors are generated per cycle! An error is generated in 1 bit out of 10 data terminals. As for which one bit among the plurality of Ilo data terminals is selected, there is a method as an algorithm, such as incrementing or decrementing the I10 data terminal that generates an error every cycle.

The 2-bit error generation generates an error in 2 bits of the plurality of I10 data terminals every cycle. As for which two bits of the plurality of Ilo data terminals are selected, the algorithm is such that, for example, the I10 data terminal that generates an error is incremented or decremented every cycle.

1/2 bit error generation is, for example, generating an error 9 in one bit of the plurality of Ilo data terminals in odd cycles, and generating an error 9 in one bit of the plurality of I10 data terminals in the even cycles.
Generate errors in bits.

FIG. 3 is an explanatory diagram showing error generated bits for each cycle in the case of erroneous generation of 1 bit or 2 pins when there are 8 I10 data terminals. In FIG. 3, 1 indicates an Ilo data terminal that has generated error data, and 0 indicates an Ilo data terminal that outputs correct read data.

As shown in Figure 3, if an error is generated in one pin out of multiple Ilo data terminals in an odd numbered cycle, and an error is generated in 2 bits out of multiple Ilo data terminals in an even numbered cycle, 16 The same error will occur in one cycle.

In this way, error data can be easily generated during reading using an external terminal without rewriting written data. Furthermore, by predetermining the error generation algorithm generated by the error generation terminal, it is possible to easily recognize which cycle and which bit of data is an error.

Effects of the Invention As described above, when a memory system is configured using the semiconductor memory of the present invention, a functional test for error correction used in the memory system can be easily performed by adding a small amount of hardware. . Particularly in the case of semiconductor memories, which are becoming larger in capacity, the addition of such functions can significantly improve the time required for functional testing of memory systems.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the semiconductor memory of the present invention, and FIG.
FIG. 3 is a block diagram of a conventional semiconductor memory, and FIG. 3 is an explanatory diagram showing an example of 1-bit or 2-bit error generation in the semiconductor memory of the present invention. 2... Row address buffer, 4... Row decoder, 6... Memory cell array, 8...
...Sense amplifier and write circuit, 1o...
Column decoder, 12...Column address buffer, 1
4... Input data control circuit, 16...
Input data bus sofa, 18... Output data bus sofa, 20... Operation control circuit, 22...
・Row address terminal, 24...Column address terminal,
26... Input/output data terminal, 28...
Write operation control terminal, 30...Chip selection terminal, 32...Output control terminal, 34...Error data generation circuit, 36, 38...Error data generation terminal. Figure 1 L2 Figure z8 J”, 32 Ta I+7)
LIILS+Figure 3

Claims (1)

[Claims] a plurality of input/output data terminals, a means for reading inverted data of 1 bit or 2 bits of stored data for each readout as a test function during a read operation; and the means. A semiconductor memory characterized by comprising: control means for controlling by a control terminal.