JPS5447439A - Memory unit - Google Patents

Memory unit

Info

Publication number
JPS5447439A
JPS5447439A JP11271277A JP11271277A JPS5447439A JP S5447439 A JPS5447439 A JP S5447439A JP 11271277 A JP11271277 A JP 11271277A JP 11271277 A JP11271277 A JP 11271277A JP S5447439 A JPS5447439 A JP S5447439A
Authority
JP
Japan
Prior art keywords
bit
writing information
test
information bit
error
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11271277A
Other languages
Japanese (ja)
Inventor
Seiji Izumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP11271277A priority Critical patent/JPS5447439A/en
Publication of JPS5447439A publication Critical patent/JPS5447439A/en
Pending legal-status Critical Current

Links

Landscapes

  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE: To avoid the rewriting to enhance the reliability as well as to lower the cost through reduction of the hard quantity, by having a parity check for the writing information bit when writing and also producing and memorizing the 1-bit error test bit.
CONSTITUTION: In case the information bit of two bytes is written into the memory unit through the external logic circuit, data selector circuits 33W37 select 16 bits of constant bit 30 and the writing information bit plus two bits of the parity test bit to store them into data registers 38W42. Then the parity test is carried out for the writing information bit with every byte through parity test bit generation/test circuit 44 and 45 and by means of writing information bit 39 and 41 plus parity test bit 40 and 42. If some error is detected, the error is informed to the outer logic unit from output line 29 through logical sum 13 secured. At the same time, the 1-bit error test bit is produced (43) newly via 16 bits of writing information bit 39 and 41 plus constant bit 30 stored in register 38, and then written into memory medium M15 along with the writing information bit
COPYRIGHT: (C)1979,JPO&Japio
JP11271277A 1977-09-21 1977-09-21 Memory unit Pending JPS5447439A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11271277A JPS5447439A (en) 1977-09-21 1977-09-21 Memory unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11271277A JPS5447439A (en) 1977-09-21 1977-09-21 Memory unit

Publications (1)

Publication Number Publication Date
JPS5447439A true JPS5447439A (en) 1979-04-14

Family

ID=14593606

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11271277A Pending JPS5447439A (en) 1977-09-21 1977-09-21 Memory unit

Country Status (1)

Country Link
JP (1) JPS5447439A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5839009A (en) * 1992-09-14 1998-11-17 Olympus Optical Co. Ltd. Camera having data imprinting function

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5839009A (en) * 1992-09-14 1998-11-17 Olympus Optical Co. Ltd. Camera having data imprinting function

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