JPS6410323A - Arithmetically computing apparatus - Google Patents
Arithmetically computing apparatusInfo
- Publication number
- JPS6410323A JPS6410323A JP63119426A JP11942688A JPS6410323A JP S6410323 A JPS6410323 A JP S6410323A JP 63119426 A JP63119426 A JP 63119426A JP 11942688 A JP11942688 A JP 11942688A JP S6410323 A JPS6410323 A JP S6410323A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- operand
- arithmetic
- multibytes
- inputted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
- G06F2207/3804—Details
- G06F2207/3808—Details concerning the type of numbers or the way they are handled
- G06F2207/3812—Devices capable of handling different types of numbers
- G06F2207/382—Reconfigurable for different fixed word lengths
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Pure & Applied Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- Mathematical Optimization (AREA)
- General Engineering & Computer Science (AREA)
- Executing Machine-Instructions (AREA)
- Complex Calculations (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/066,580 US4914617A (en) | 1987-06-26 | 1987-06-26 | High performance parallel binary byte adder |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6410323A true JPS6410323A (en) | 1989-01-13 |
JPH0542012B2 JPH0542012B2 (ja) | 1993-06-25 |
Family
ID=22070409
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63119426A Granted JPS6410323A (en) | 1987-06-26 | 1988-05-18 | Arithmetically computing apparatus |
Country Status (3)
Country | Link |
---|---|
US (1) | US4914617A (ja) |
EP (1) | EP0296457A3 (ja) |
JP (1) | JPS6410323A (ja) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5189636A (en) * | 1987-11-16 | 1993-02-23 | Intel Corporation | Dual mode combining circuitry |
US5333287A (en) * | 1988-12-21 | 1994-07-26 | International Business Machines Corporation | System for executing microinstruction routines by using hardware to calculate initialization parameters required therefore based upon processor status and control parameters |
JP2504156B2 (ja) * | 1989-01-25 | 1996-06-05 | 日本電気株式会社 | 情報処理装置 |
US5327368A (en) * | 1989-06-23 | 1994-07-05 | Digital Equipment Corporation | Chunky binary multiplier and method of operation |
JP2601960B2 (ja) * | 1990-11-15 | 1997-04-23 | インターナショナル・ビジネス・マシーンズ・コーポレイション | データ処理方法及びその装置 |
FR2693287B1 (fr) * | 1992-07-03 | 1994-09-09 | Sgs Thomson Microelectronics Sa | Procédé pour effectuer des calculs numériques, et unité arithmétique pour la mise en Óoeuvre de ce procédé. |
US5327369A (en) * | 1993-03-31 | 1994-07-05 | Intel Corporation | Digital adder and method for adding 64-bit, 16-bit and 8-bit words |
US5883824A (en) * | 1993-11-29 | 1999-03-16 | Hewlett-Packard Company | Parallel adding and averaging circuit and method |
US5390135A (en) * | 1993-11-29 | 1995-02-14 | Hewlett-Packard | Parallel shift and add circuit and method |
US6016538A (en) * | 1993-11-30 | 2000-01-18 | Texas Instruments Incorporated | Method, apparatus and system forming the sum of data in plural equal sections of a single data word |
US5596763A (en) * | 1993-11-30 | 1997-01-21 | Texas Instruments Incorporated | Three input arithmetic logic unit forming mixed arithmetic and boolean combinations |
US5719802A (en) * | 1995-12-22 | 1998-02-17 | Chromatic Research, Inc. | Adder circuit incorporating byte boundaries |
US5835782A (en) * | 1996-03-04 | 1998-11-10 | Intel Corporation | Packed/add and packed subtract operations |
US6003125A (en) * | 1997-01-24 | 1999-12-14 | Texas Instruments Incorporated | High performance adder for multiple parallel add operations |
US20030065696A1 (en) * | 2001-09-28 | 2003-04-03 | Ruehle Michael D. | Method and apparatus for performing modular exponentiation |
US6922717B2 (en) | 2001-09-28 | 2005-07-26 | Intel Corporation | Method and apparatus for performing modular multiplication |
EP2181504A4 (en) * | 2008-08-15 | 2010-07-28 | Lsi Corp | DECODING LIST OF CODED WORDS CLOSE IN A ROM MEMORY |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5827241A (ja) * | 1981-08-12 | 1983-02-17 | Hitachi Ltd | 十進演算装置 |
JPS60229139A (ja) * | 1984-04-25 | 1985-11-14 | Nec Corp | 10進演算装置 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1245441A (en) * | 1968-08-27 | 1971-09-08 | Int Computers Ltd | Improvements in or relating to adders operating on variable fields within words |
US3987291A (en) * | 1975-05-01 | 1976-10-19 | International Business Machines Corporation | Parallel digital arithmetic device having a variable number of independent arithmetic zones of variable width and location |
US4021655A (en) * | 1976-03-30 | 1977-05-03 | International Business Machines Corporation | Oversized data detection hardware for data processors which store data at variable length destinations |
JPS5824941A (ja) * | 1981-08-07 | 1983-02-15 | Hitachi Ltd | 演算装置 |
JPS6055438A (ja) * | 1983-09-05 | 1985-03-30 | Matsushita Electric Ind Co Ltd | 2入力加算器 |
-
1987
- 1987-06-26 US US07/066,580 patent/US4914617A/en not_active Expired - Fee Related
-
1988
- 1988-05-18 JP JP63119426A patent/JPS6410323A/ja active Granted
- 1988-06-14 EP EP19880109439 patent/EP0296457A3/en not_active Withdrawn
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5827241A (ja) * | 1981-08-12 | 1983-02-17 | Hitachi Ltd | 十進演算装置 |
JPS60229139A (ja) * | 1984-04-25 | 1985-11-14 | Nec Corp | 10進演算装置 |
Also Published As
Publication number | Publication date |
---|---|
EP0296457A3 (en) | 1991-07-17 |
US4914617A (en) | 1990-04-03 |
JPH0542012B2 (ja) | 1993-06-25 |
EP0296457A2 (en) | 1988-12-28 |
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