JPS5622169A - Control system of array processor - Google Patents

Control system of array processor

Info

Publication number
JPS5622169A
JPS5622169A JP9796679A JP9796679A JPS5622169A JP S5622169 A JPS5622169 A JP S5622169A JP 9796679 A JP9796679 A JP 9796679A JP 9796679 A JP9796679 A JP 9796679A JP S5622169 A JPS5622169 A JP S5622169A
Authority
JP
Japan
Prior art keywords
pipe line
mask
sent
bit
mpl
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9796679A
Other languages
Japanese (ja)
Inventor
Masanori Mogi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9796679A priority Critical patent/JPS5622169A/en
Publication of JPS5622169A publication Critical patent/JPS5622169A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To ensure an effective processing for two types of operations, by by- passing the output side of the mask pipe line MPL of one side at several arithmetic process parts having both the operation pipe line and the mask pipe line MPL to the input side of the MPL of the other side.
CONSTITUTION: When the ADD instruction is set to addition instruction execution register 1, the set of the data elements and the mask bits (Ai, Bi, Mi), where i means 1... n, is supplied successively to addition pipe line 9 and MPL9a. Then the sum of the data elements Ai+Bi plus mask bit Mi are delivered from pipe lines 9 and 9a each to be sent to designated vector register 5. At the same time, bit Mi is sent to MPL10a through by-pass circiut part BP. When bit Mi is supplied to MPL10a, elements Ai' and Bi' of the vector designated by the 2nd and 3rd operands R2' and R3' of the MULTIPLY instruction are sent to multiplication pipe line 10. As a result, both the addition and the multiplication can be carried out simultaneously via the same mask register 6.
COPYRIGHT: (C)1981,JPO&Japio
JP9796679A 1979-07-31 1979-07-31 Control system of array processor Pending JPS5622169A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9796679A JPS5622169A (en) 1979-07-31 1979-07-31 Control system of array processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9796679A JPS5622169A (en) 1979-07-31 1979-07-31 Control system of array processor

Publications (1)

Publication Number Publication Date
JPS5622169A true JPS5622169A (en) 1981-03-02

Family

ID=14206402

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9796679A Pending JPS5622169A (en) 1979-07-31 1979-07-31 Control system of array processor

Country Status (1)

Country Link
JP (1) JPS5622169A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4621255A (en) * 1983-10-20 1986-11-04 Fujitsu Ten Limited Method and apparatus for analog-to-digital conversion

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4621255A (en) * 1983-10-20 1986-11-04 Fujitsu Ten Limited Method and apparatus for analog-to-digital conversion

Similar Documents

Publication Publication Date Title
US4748580A (en) Multi-precision fixed/floating-point processor
JPS5533280A (en) Data processing system
US4775952A (en) Parallel processing system apparatus
JPS5622169A (en) Control system of array processor
JPS5378742A (en) Multiplication control system
JPS5663649A (en) Parallel multiplication apparatus
JPS5621246A (en) Pipeline control system
JPS57113144A (en) Stored program computer
ES8506955A1 (en) A self routing steering network.
JPS5696330A (en) Multiplication control system
JPS5386539A (en) Arithmetic unit
JPS6433672A (en) Cumulative multiplier
JPS5622168A (en) Control system of array processor
JPS5687133A (en) Electronic apparatus
JPS5696339A (en) Data processing system
JPS569846A (en) Instruction retry system
JPS54132144A (en) Multiple process system
JPS5580152A (en) Multiplication system
SU962973A1 (en) Device for computing polynomial values
JPS55108051A (en) Buffer system for data in multiplier
JPS5619142A (en) Arithmetic control system
JPS5647840A (en) Arithmetic unit
JPS57117065A (en) Vector processing system
JPS61253538A (en) Arithmetic circuit
JPS5789126A (en) Data transfer control system