JPS5622169A - Control system of array processor - Google Patents
Control system of array processorInfo
- Publication number
- JPS5622169A JPS5622169A JP9796679A JP9796679A JPS5622169A JP S5622169 A JPS5622169 A JP S5622169A JP 9796679 A JP9796679 A JP 9796679A JP 9796679 A JP9796679 A JP 9796679A JP S5622169 A JPS5622169 A JP S5622169A
- Authority
- JP
- Japan
- Prior art keywords
- pipe line
- mask
- sent
- bit
- mpl
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE: To ensure an effective processing for two types of operations, by by- passing the output side of the mask pipe line MPL of one side at several arithmetic process parts having both the operation pipe line and the mask pipe line MPL to the input side of the MPL of the other side.
CONSTITUTION: When the ADD instruction is set to addition instruction execution register 1, the set of the data elements and the mask bits (Ai, Bi, Mi), where i means 1... n, is supplied successively to addition pipe line 9 and MPL9a. Then the sum of the data elements Ai+Bi plus mask bit Mi are delivered from pipe lines 9 and 9a each to be sent to designated vector register 5. At the same time, bit Mi is sent to MPL10a through by-pass circiut part BP. When bit Mi is supplied to MPL10a, elements Ai' and Bi' of the vector designated by the 2nd and 3rd operands R2' and R3' of the MULTIPLY instruction are sent to multiplication pipe line 10. As a result, both the addition and the multiplication can be carried out simultaneously via the same mask register 6.
COPYRIGHT: (C)1981,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9796679A JPS5622169A (en) | 1979-07-31 | 1979-07-31 | Control system of array processor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9796679A JPS5622169A (en) | 1979-07-31 | 1979-07-31 | Control system of array processor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5622169A true JPS5622169A (en) | 1981-03-02 |
Family
ID=14206402
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9796679A Pending JPS5622169A (en) | 1979-07-31 | 1979-07-31 | Control system of array processor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5622169A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4621255A (en) * | 1983-10-20 | 1986-11-04 | Fujitsu Ten Limited | Method and apparatus for analog-to-digital conversion |
-
1979
- 1979-07-31 JP JP9796679A patent/JPS5622169A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4621255A (en) * | 1983-10-20 | 1986-11-04 | Fujitsu Ten Limited | Method and apparatus for analog-to-digital conversion |
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