JPS5619142A - Arithmetic control system - Google Patents

Arithmetic control system

Info

Publication number
JPS5619142A
JPS5619142A JP9436879A JP9436879A JPS5619142A JP S5619142 A JPS5619142 A JP S5619142A JP 9436879 A JP9436879 A JP 9436879A JP 9436879 A JP9436879 A JP 9436879A JP S5619142 A JPS5619142 A JP S5619142A
Authority
JP
Japan
Prior art keywords
register
data
multiplexers
input
control information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9436879A
Other languages
Japanese (ja)
Inventor
Osamu Suzuki
Matsuo Shironaga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9436879A priority Critical patent/JPS5619142A/en
Publication of JPS5619142A publication Critical patent/JPS5619142A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To enable initializing effectively with a simple method when the control information is set to the control register, by providing the initializing set which initializes the arithmetic output data register and the arithmetic input data register.
CONSTITUTION: The system is provided with the arithmetic result register 1 to which the operation output data is set, a plurality of multiplicand registers 2, multiplication register 3 and control register 4 to which the control data is set, and the write signal from the signal line l and the control information are added to the register 4. Further, the multiplexers 5W7 are connected to the registers 1W3, and the write signal and the data are input to the multiplexers 5W7. Further, all 0 data is input to the multiplexers 5W7, the control information is fed to the register 4, the signal line l is taken as 1, the control information is set to the register 4, and 0 data is input to the multiplexers 5W7 with 1 on the signal line l at the same time, to effectively initialize the registers 1W3.
COPYRIGHT: (C)1981,JPO&Japio
JP9436879A 1979-07-25 1979-07-25 Arithmetic control system Pending JPS5619142A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9436879A JPS5619142A (en) 1979-07-25 1979-07-25 Arithmetic control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9436879A JPS5619142A (en) 1979-07-25 1979-07-25 Arithmetic control system

Publications (1)

Publication Number Publication Date
JPS5619142A true JPS5619142A (en) 1981-02-23

Family

ID=14108367

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9436879A Pending JPS5619142A (en) 1979-07-25 1979-07-25 Arithmetic control system

Country Status (1)

Country Link
JP (1) JPS5619142A (en)

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