JPS5647840A - Arithmetic unit - Google Patents

Arithmetic unit

Info

Publication number
JPS5647840A
JPS5647840A JP12422179A JP12422179A JPS5647840A JP S5647840 A JPS5647840 A JP S5647840A JP 12422179 A JP12422179 A JP 12422179A JP 12422179 A JP12422179 A JP 12422179A JP S5647840 A JPS5647840 A JP S5647840A
Authority
JP
Japan
Prior art keywords
data
latched
arithmetic unit
buses
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12422179A
Other languages
Japanese (ja)
Inventor
Misao Miyata
Masahide Ohashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP12422179A priority Critical patent/JPS5647840A/en
Publication of JPS5647840A publication Critical patent/JPS5647840A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To release an input data line and make it possible to perform the operation or processing by other operator in parallel, by latching an input data.
CONSTITUTION: The microinstruction for designating the operation of a multiplier 12 is set to the register 20. An operation data is provided to the buses 10 and 11 by a control signal from the control part 17. This data is latched to the data latch circuits 15, 16. While the data is being latched, the operation designated from the control part 17 is executed. On the other hand, while the data is being latched by the latch circuits 15, 16, the buses 10, 11 are released, and when the operation designating instruction of the arithmetic unit (ALU) 13 is set to the register 20 before execution of the aforesaid operation is finished, ALU13 executes this operation. Thus, the parallel operation can be performed.
COPYRIGHT: (C)1981,JPO&Japio
JP12422179A 1979-09-28 1979-09-28 Arithmetic unit Pending JPS5647840A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12422179A JPS5647840A (en) 1979-09-28 1979-09-28 Arithmetic unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12422179A JPS5647840A (en) 1979-09-28 1979-09-28 Arithmetic unit

Publications (1)

Publication Number Publication Date
JPS5647840A true JPS5647840A (en) 1981-04-30

Family

ID=14879983

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12422179A Pending JPS5647840A (en) 1979-09-28 1979-09-28 Arithmetic unit

Country Status (1)

Country Link
JP (1) JPS5647840A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60157631A (en) * 1983-12-27 1985-08-17 エヌ・ベー・フイリツプス・フルーイランペンフアブリケン Integrated programmable processor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60157631A (en) * 1983-12-27 1985-08-17 エヌ・ベー・フイリツプス・フルーイランペンフアブリケン Integrated programmable processor

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