JPS5696330A - Multiplication control system - Google Patents
Multiplication control systemInfo
- Publication number
- JPS5696330A JPS5696330A JP17318279A JP17318279A JPS5696330A JP S5696330 A JPS5696330 A JP S5696330A JP 17318279 A JP17318279 A JP 17318279A JP 17318279 A JP17318279 A JP 17318279A JP S5696330 A JPS5696330 A JP S5696330A
- Authority
- JP
- Japan
- Prior art keywords
- multiplier
- multiplication
- processing unit
- central processing
- common bus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE: To perform the multiplication of all 0 (zeroes) in a high speed, by transferring the multiplier and the mutliplicand to a multiplier and by reporting to the multiplier that either of them at least is all 0 (zeroes) when it is detected in the course of multiplication.
CONSTITUTION: The multiplier and the multiplicand entered in the work register in a central processing unit are sent through common bus 3, and the multiplication result by multiplier 1 is returned to the central processing unit through common bus 4. When either of the multiplicand or the multiplier transmitted through the common bus is True 0, it is detected by zero detecting circuit 2 and is transferred to multiplier control part 1W1, and the multiplication stop is instructed. Multiplier 1 discontinues the processing which has been processed, and True 0 is set to the destination area in the central processing unit.
COPYRIGHT: (C)1981,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17318279A JPS5696330A (en) | 1979-12-28 | 1979-12-28 | Multiplication control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17318279A JPS5696330A (en) | 1979-12-28 | 1979-12-28 | Multiplication control system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5696330A true JPS5696330A (en) | 1981-08-04 |
Family
ID=15955605
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17318279A Pending JPS5696330A (en) | 1979-12-28 | 1979-12-28 | Multiplication control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5696330A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63198126A (en) * | 1987-02-13 | 1988-08-16 | Hitachi Denshi Ltd | Arithmetic processing circuit |
JPS6461821A (en) * | 1987-09-02 | 1989-03-08 | Matsushita Electric Ind Co Ltd | Multiplication circuit |
JPH02100127A (en) * | 1988-10-06 | 1990-04-12 | Nec Corp | Data processor |
JPH06342367A (en) * | 1993-06-01 | 1994-12-13 | Nec Corp | Multiplying circuit |
-
1979
- 1979-12-28 JP JP17318279A patent/JPS5696330A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63198126A (en) * | 1987-02-13 | 1988-08-16 | Hitachi Denshi Ltd | Arithmetic processing circuit |
JPS6461821A (en) * | 1987-09-02 | 1989-03-08 | Matsushita Electric Ind Co Ltd | Multiplication circuit |
JPH02100127A (en) * | 1988-10-06 | 1990-04-12 | Nec Corp | Data processor |
JPH06342367A (en) * | 1993-06-01 | 1994-12-13 | Nec Corp | Multiplying circuit |
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