JPS6461821A - Multiplication circuit - Google Patents

Abstract

PURPOSE:To carry out the multiplication including codes at a high speed by shifting sequentially a multiplier toward the minimum position bit to hold it after totalizing sequentially the partial products and deciding whether all bits of the shifted multiplier are equal to '0' or '1' to decided the end of the totalization. CONSTITUTION:At the outset a multiplier is supplied to a multiplier register 1 together with a multiplicand supplied to a multiplicand register 4, and the triple value of the multiplicand supplied to a multiplicand triple value register 5 respectively. An arithmetic control circuit 11a decodes the low-order 3 bits of the register 1 and total 4 bits of a carrier flag 3 to decide the selection of a selection circuit 6a, the shift number of a barrel shifter 7 and the arithmetic of an arithmetic circuit 9. The circuit 6a selects the triple values of both the multiplier and the multiplicand. The circuit 9 calculates the partial product held by a partial product register 8 and the output of the shifter 7. An end deciding circuit 12 repeats its processing until it is detected that all bits of the register 1 are equal to '0' or '1' and holds the result of multiplication in the register 8. Thus it is possible to decrease the arithmetic frequency needed for the due processing in response to the value of the multiplier.