JPS6461821A - Multiplication circuit - Google Patents

Multiplication circuit

Info

Publication number
JPS6461821A
JPS6461821A JP62219509A JP21950987A JPS6461821A JP S6461821 A JPS6461821 A JP S6461821A JP 62219509 A JP62219509 A JP 62219509A JP 21950987 A JP21950987 A JP 21950987A JP S6461821 A JPS6461821 A JP S6461821A
Authority
JP
Japan
Prior art keywords
register
multiplier
circuit
multiplicand
bits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62219509A
Other languages
Japanese (ja)
Other versions
JP2532505B2 (en
Inventor
Masato Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP62219509A priority Critical patent/JP2532505B2/en
Publication of JPS6461821A publication Critical patent/JPS6461821A/en
Application granted granted Critical
Publication of JP2532505B2 publication Critical patent/JP2532505B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To carry out the multiplication including codes at a high speed by shifting sequentially a multiplier toward the minimum position bit to hold it after totalizing sequentially the partial products and deciding whether all bits of the shifted multiplier are equal to '0' or '1' to decided the end of the totalization. CONSTITUTION:At the outset a multiplier is supplied to a multiplier register 1 together with a multiplicand supplied to a multiplicand register 4, and the triple value of the multiplicand supplied to a multiplicand triple value register 5 respectively. An arithmetic control circuit 11a decodes the low-order 3 bits of the register 1 and total 4 bits of a carrier flag 3 to decide the selection of a selection circuit 6a, the shift number of a barrel shifter 7 and the arithmetic of an arithmetic circuit 9. The circuit 6a selects the triple values of both the multiplier and the multiplicand. The circuit 9 calculates the partial product held by a partial product register 8 and the output of the shifter 7. An end deciding circuit 12 repeats its processing until it is detected that all bits of the register 1 are equal to '0' or '1' and holds the result of multiplication in the register 8. Thus it is possible to decrease the arithmetic frequency needed for the due processing in response to the value of the multiplier.
JP62219509A 1987-09-02 1987-09-02 Multiplication circuit Expired - Fee Related JP2532505B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62219509A JP2532505B2 (en) 1987-09-02 1987-09-02 Multiplication circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62219509A JP2532505B2 (en) 1987-09-02 1987-09-02 Multiplication circuit

Publications (2)

Publication Number Publication Date
JPS6461821A true JPS6461821A (en) 1989-03-08
JP2532505B2 JP2532505B2 (en) 1996-09-11

Family

ID=16736574

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62219509A Expired - Fee Related JP2532505B2 (en) 1987-09-02 1987-09-02 Multiplication circuit

Country Status (1)

Country Link
JP (1) JP2532505B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4966803A (en) * 1987-07-23 1990-10-30 Stamicarbon, B.V. Polymer films partially provided with stiffened segments, process for the production thereof, and the use thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5378742A (en) * 1976-12-23 1978-07-12 Toshiba Corp Multiplication control system
JPS5696330A (en) * 1979-12-28 1981-08-04 Fujitsu Ltd Multiplication control system
JPS59229644A (en) * 1983-06-10 1984-12-24 Nec Corp Multiplier
JPS63198125A (en) * 1987-02-13 1988-08-16 Nec Corp Multiplication circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5378742A (en) * 1976-12-23 1978-07-12 Toshiba Corp Multiplication control system
JPS5696330A (en) * 1979-12-28 1981-08-04 Fujitsu Ltd Multiplication control system
JPS59229644A (en) * 1983-06-10 1984-12-24 Nec Corp Multiplier
JPS63198125A (en) * 1987-02-13 1988-08-16 Nec Corp Multiplication circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4966803A (en) * 1987-07-23 1990-10-30 Stamicarbon, B.V. Polymer films partially provided with stiffened segments, process for the production thereof, and the use thereof

Also Published As

Publication number Publication date
JP2532505B2 (en) 1996-09-11

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees