JPS5757340A - Arithmetic system - Google Patents

Arithmetic system

Info

Publication number
JPS5757340A
JPS5757340A JP55131966A JP13196680A JPS5757340A JP S5757340 A JPS5757340 A JP S5757340A JP 55131966 A JP55131966 A JP 55131966A JP 13196680 A JP13196680 A JP 13196680A JP S5757340 A JPS5757340 A JP S5757340A
Authority
JP
Japan
Prior art keywords
arithmetic
result
decimal
transmitted
compensating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55131966A
Other languages
Japanese (ja)
Inventor
Nobuyuki Baba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55131966A priority Critical patent/JPS5757340A/en
Publication of JPS5757340A publication Critical patent/JPS5757340A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/491Computations with decimal numbers radix 12 or 20.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)

Abstract

PURPOSE:To realize high-speed decimal arithmetic without increasing the quantity of hardware, by having a binary arithmetic part and a compensating arithmetic part to carry out simultaneous arithmetic in a decimal arithmetic system that performs arithmetic by adding compensating arithmetic to a calculated numerical value. CONSTITUTION:A binary arithmetic part 12 performs arithmetic based on the numerical value set to arithmetic input registers 15 and 16, and the result of this arithmetic is delivered to an arithmetic output register 17. When the result of arithmetic of the part 12 is 10, a signal (k) is produced to set the necessary compensated value at a compensated value setting part 14. The output of the register 17 is transmitted to a multiplexer (MPX)18, and the compensated value given from the part 14 is transmitted to an MPX19. The numerical values given from the MPXs 18 and 19 are calculated at a compensating arithmetic part 13, and this result of arithmetic is delivered to an arithmetic register 22. When delivering the numerical values transmitted from arithmetic input registers 20 and 21, the MPXs 18 and 19 perform arithmetic based on these values. Both the parts 12 and 13 carry out the arithmetic at a time, and as a result, decimal arithmetic can be performed at a high speed.
JP55131966A 1980-09-22 1980-09-22 Arithmetic system Pending JPS5757340A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55131966A JPS5757340A (en) 1980-09-22 1980-09-22 Arithmetic system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55131966A JPS5757340A (en) 1980-09-22 1980-09-22 Arithmetic system

Publications (1)

Publication Number Publication Date
JPS5757340A true JPS5757340A (en) 1982-04-06

Family

ID=15070380

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55131966A Pending JPS5757340A (en) 1980-09-22 1980-09-22 Arithmetic system

Country Status (1)

Country Link
JP (1) JPS5757340A (en)

Similar Documents

Publication Publication Date Title
JPS6410323A (en) Arithmetically computing apparatus
GB747711A (en) Improvements in digital calculating machines
JPS54159831A (en) Adder and subtractor for numbers different in data length using counter circuit
JPS5757340A (en) Arithmetic system
JPS5446463A (en) Pre-scaler
JPS54154964A (en) Programable counter
JPS5351936A (en) High speed addition circuit
GB1287845A (en)
JPS5685127A (en) Digital signal processor
JPS5663649A (en) Parallel multiplication apparatus
JPS57191753A (en) Register controlling system
JPS53138667A (en) A/d converter circuit
JPS6442733A (en) Adder using 2m-a as modulus
GB948314A (en) Improvements in or relating to adding mechanism
JPS6476221A (en) Logical operating circuit
JPS5696328A (en) Logical arithmetic operating device
JPS6444576A (en) Arithmetic circuit
JPS57130149A (en) System for interruption processing of microprogram control device
JPS6412331A (en) Arithmetic circuit
JPS6433672A (en) Cumulative multiplier
JPS5764864A (en) Digital arithmetic circuit
FR2356205A3 (en) System for rapid division of floating point numbers - applies intermediate corrections during calculation to provide high speed precise division
JPS5785142A (en) Random number generating circuit
JPS5765047A (en) Split phase type data generating system
JPS5729149A (en) Decimal arithmetic system