JPS639704B2 - - Google Patents

Info

Publication number
JPS639704B2
JPS639704B2 JP56027501A JP2750181A JPS639704B2 JP S639704 B2 JPS639704 B2 JP S639704B2 JP 56027501 A JP56027501 A JP 56027501A JP 2750181 A JP2750181 A JP 2750181A JP S639704 B2 JPS639704 B2 JP S639704B2
Authority
JP
Japan
Prior art keywords
output
circuit
switch
phase
full
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56027501A
Other languages
English (en)
Japanese (ja)
Other versions
JPS57141157A (en
Inventor
Akihide Nishama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56027501A priority Critical patent/JPS57141157A/ja
Publication of JPS57141157A publication Critical patent/JPS57141157A/ja
Publication of JPS639704B2 publication Critical patent/JPS639704B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/027—Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP56027501A 1981-02-26 1981-02-26 Clock regenerating circuit Granted JPS57141157A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56027501A JPS57141157A (en) 1981-02-26 1981-02-26 Clock regenerating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56027501A JPS57141157A (en) 1981-02-26 1981-02-26 Clock regenerating circuit

Publications (2)

Publication Number Publication Date
JPS57141157A JPS57141157A (en) 1982-09-01
JPS639704B2 true JPS639704B2 (enrdf_load_stackoverflow) 1988-03-01

Family

ID=12222889

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56027501A Granted JPS57141157A (en) 1981-02-26 1981-02-26 Clock regenerating circuit

Country Status (1)

Country Link
JP (1) JPS57141157A (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3719413B2 (ja) 2001-12-05 2005-11-24 日本電気株式会社 データ伝送システム及びそれに用いられるデータ送受信装置と、その方法

Also Published As

Publication number Publication date
JPS57141157A (en) 1982-09-01

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