JPS639704B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clock recovery circuit that recovers a clock from split code format data.

A conventional clock regeneration circuit will be explained with reference to FIGS. 1 and 2.

In FIG. 1, data in a split code format as shown in FIG. The waveform will look like this. The band wave generator 4 outputs only the fundamental frequency component as shown in FIG. 2 from this differential waveform and inputs it to the comparator 5. The comparator 5 compares the reference level and the fundamental frequency component, outputs a pulse as shown in FIG. 2, and inputs it to the digital PLL circuit 6. The digital PLL circuit 6 outputs a pulse that is phase synchronized with the input pulse. Although this allows the reproduction of a clock synchronized with input data, this circuit has the following drawbacks. In other words, as shown in Fig. 2, when a certain number or more of data of "0" or "1" continues, the output of the bandpass converter 4 (Fig. 2) no longer crosses the reference level TH at T ₁ or T ₂ . , there was a drawback that the output of the comparator 5 was inverted at T ₁ and T ₂ .

The present invention aims to eliminate such drawbacks, and the purpose is to provide a differentiating circuit for differentiating split code format data, a full-wave rectifier circuit for full-wave rectifying the output of the differentiating circuit, and A band wave generator extracts a specific frequency component from the output from the full wave rectifier, and a clock regeneration circuit inputs the output of the band wave generator to a phase synchronized circuit and outputs a clock synchronized with the input data. A switch is provided between the wave rectifier circuit and the band wave generator, and a level detector is provided to detect the level of the output of the switch,
The switch is turned on and off in synchronization with the output of the phase-locked circuit, and when the level detector detects that the level of the switch output is below or above a predetermined value, the output phase of the phase-locked circuit is turned on and off. This is accomplished by a clock recovery circuit that controls the clock.

Hereinafter, the present invention will be explained in detail based on examples.

FIG. 3 shows an embodiment of the present invention, in which 7 is a switch, 8 is a level detector, 9 is a comparator, and 10 is a reset pulse generator, and the same members as in FIG. 1 are given the same symbols. There is.

In FIG. 3, the same operations as in FIG. 1 are performed up to the full-wave rectifier circuit 3. The difference is that a switch 7 that turns on and off in synchronization with the output of the digital PLL is provided at the output stage of the full-wave rectifier circuit 3, and the differential pulse input to the bandpass converter 4 is thinned out, and the average level of the output of the switch 7 is is detected by the level detector 8, and this average level is compared with the reference level by the comparator. When the average level becomes lower than the reference level, the reset pulse generator 10 is driven to generate a reset pulse, and the digital The point is that the PLL is reset. Therefore, even if "0" or "1" is input continuously, the fundamental frequency component of the differential pulse input to the bandpass converter 4 matches the center frequency of the bandpass converter 4, and as in the conventional case, No phase reversal occurs.

The above will be further explained using FIGS. 4 and 5.

In FIG. 4, the output of the full-wave rectifier circuit 3 is:
When the signal is input to the switch 7, it is thinned out by AND with the output of the digital PLL 6 as shown in FIG.
This output is sequentially input to the band wave generator 4, the comparator 5, and the digital PLL 6 as in the conventional case. Further, the average level of the output of the switch 7 is outputted from the level detector 8, and is compared with a reference level in the comparator 9.

As shown in the figure, if the output phase of the digital PLL is synchronized with the rising edge of the input data, switch 7
Since differential pulses are outputted synchronously as shown, the output of the level detector 8 becomes high level as shown, and the output of the comparator also becomes high level.
Therefore, the reset pulse generator 10 does not generate a reset pulse. On the other hand, when the output phase of the digital PLL 6 is synchronized with the falling edge of the input data as shown in FIG. Since the differential pulse is output as shown in
Since the band wave generator 4 outputs a signal as shown in ', at a certain time _T3 , the output ' of the comparator is inverted, and a reset pulse synchronized with the immediately following clock is generated, thereby causing the digital
PLL6 is strongly inverted and its output phase is shifted to the correct phase. As a result, switch 7 is supplied with a clock of the correct phase. Therefore,
The output of switch 7 becomes a pulse train with a constant period,
The output of the level detector 8 rises, and the output of the comparator 9 recognizes this and returns to "1", resulting in the operation shown in FIG. 4, making it possible to recover even if the phase is shifted.

As described above, according to the present invention, there is no phase inversion caused by the pattern of input data, and even if the phase shifts due to some reason, it can be corrected.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a conventional clock recovery circuit.
Figure 2 is a time chart of the circuit in Figure 1;
Figure 4 shows a clock regeneration circuit according to the present invention.
5 is a time chart of the circuit shown in FIG. In the figure, 1 is an amplitude limiting circuit, 2 is a differentiator circuit, 3 is a full-wave rectifier circuit, 4 is a band wave generator, 5, 9
is a comparator, 6 is a digital PLL, 7 is a switch,
8 is a level detector, and 10 is a reset pulse generator.

Claims (1)

[Claims] 1. A differentiating circuit that performs differentiation of data in split code format, a full-wave rectifier circuit that performs full-wave rectification of the output of the differentiating circuit, a bandpass filter that extracts a specific frequency component from the output from the full-wave rectifier circuit, and a In a clock regeneration circuit that inputs the output of a band wave generator to a phase locked circuit and outputs a clock synchronized with the input data, a switch is provided between the full wave rectifier circuit and the band wave generator, and the level of the output of the switch is A level detector is provided to detect the switch, and the switch is turned on and off in synchronization with the output of the phase-locked circuit, and when the level detector detects that the level of the switch output is below or above a predetermined value. , a clock regeneration circuit configured to control the output phase of the phase synchronized circuit.