JPS59110256A - Reference carrier wave regenerating circuit of two-phase demodulator - Google Patents

Abstract

PURPOSE:To eliminate the need to multiply an input modulated wave by two, and to realize a digital circuit constitution and to attain LSI implementation by performing comparing operation only in a specific phase section of a voltage- controlled type variable frequency oscillation circuit VCO. CONSTITUTION:The PLL circuit consisting of phase comparing circuits 1-5 and 8, control voltage generating circuit 6, and a VCO7 processes a two-phase PSK modulated wave and the VCO7 regenerates a reference carrier wave. The circuits 1-5, and 8 include a comparison limiting means which performs comparing operation in a -90-+90 deg. phase section. The leading edge and trailing edge of the input modulated wave are detected in this limited period and a timing comparison with the 0 deg.-phase point of the output signal of the VCO7 is made to generates a positive or a negative integral input signal according to the timing difference. Then, the circuit 6 consists of an integration circuit which inputs the integral input and VCO7 is controlled by the integral output to regenerate a reference carrier wave.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention provides an I! ] 7.

(Prior art and its problems) A circuit that regenerates a reference carrier wave from the two-phase PSK modulated wave itself doubles the modulated wave using a square circuit, and then passes the output through a high-Q tank circuit to a stable carrier wave. The most common circuit system is to extract the second harmonic and divide its output using a 1/2 frequency divider circuit.

In this circuit, fluctuations in the input wave are removed by the high-Q tank circuit described above, but if code amount interference occurs due to the influence of the band limit of the communication channel, the intended effect of the tank circuit is no longer 1Q, and the stability becomes unstable. It is quite difficult to recover a standard carrier wave.

Also, the input modulated wave is 231! It is difficult to digitize the circuit for multiplication, and it has not been possible to convert this type of reference carrier regeneration circuit into a digital LSI.

Also known is a circuit in which the above-mentioned high Q tank circuit is replaced with a PLL (phase single loop) circuit having a long feedback time constant. However, in this case as well, since the input modulated wave itself repeats phase inversion with O1π, a circuit that doubles the input modulated wave is essential in order to perform stable phase comparison, and for this reason it cannot be implemented as a digital LSI. Ta.

(Objective of the Invention) The object of the present invention is to stably reproduce a reference carrier wave using a digital circuit technique that eliminates the need for a circuit that doubles the input carrier wave, is configured mainly with a PLL circuit, and is easily integrated into an LSI. It is an object of the present invention to provide a reference carrier regeneration circuit for a two-phase PSK demodulator that can perform the following steps.

(Structure and Effect of the Invention) In order to achieve the above object, the present invention provides two PL circuits each including a phase comparison circuit, a control voltage generation circuit, and a VCO (voltage controlled variable frequency oscillation circuit). Phase PSK
The basic configuration is to process a modulated wave and obtain a reference carrier wave from this VCO, and in particular, the phase comparison circuit is configured to process a modulated wave and obtain a reference carrier wave from this VCO.
Comparison period limiting means for performing a comparison operation only in a period of phase -90' to +90° of one cycle of the output signal of the input modulated wave; Detect the falling edge and compare the timing of the phase O0 of the output signal of the VCO.
The circuit is configured to generate a positive or negative integral input signal according to the timing difference, and the control voltage generating circuit is composed of an integrating circuit that receives the integral input, and controls the VCO with the integral output. It is characterized by being configured as follows.

” - According to the configuration described above, the two-phase PSK modulated wave is in principle 4
Regardless of the property that the phase that is 1 is repeatedly reversed, the reference carrier wave can be stably reproduced from the modulated wave. In other words, at the point where the phase of the input modulated wave is reversed, a large phase difference with the output signal from the Vco (gt\carrier wave) occurs, and the detected output of this phase difference disturbs the continuity of the phase of the VCO output signal. However, according to the structure of the present invention, even if the phase of the incoming modulated wave is reversed, the phase comparator circuit generates a relatively large phase difference detection output for only one cycle. From the next cycle, the phase comparison point of the input modulated wave changes by 180°, so the VCO
There is almost no phase difference with the output horn signal, so P
The LL circuit almost stably maintains the locked state.

Further, in the above-described configuration according to the present invention, the input modulated wave is
Since it does not include a transmitting circuit and is entirely composed of digital circuits, it can be easily integrated into an LSI.

(Description of Embodiment) FIG. 1 is a diagram showing a circuit configuration of an embodiment of the present invention, and FIG. 2 is a time chart showing signal waveforms of various parts in the same figure. The two-phase PSK modulated wave fit+ is input to the edge detection circuit 1, and a minute width pulse signal is generated in response to its rising and falling edges.The pulse signal Δfrn is input to the king input of the D-type flip-flop Otub 2. applied. Figure 2 shows the input modulated wave f in and edge detection circuit 1.
shows the relationship between the output Δf iyl. In this figure, T1 and T2 have the phase of the input modulated wave f in of 18
The output signal △f;n of the edge detection circuit 1 is a pulse train with a period of 1/2 of the period of flll in the section where the phase of the incoming horn modulated wave f in is not inverted. However, once the phase of the input modulated wave f in is inverted, one pulse is lost at the inversion point.

The VCO 7 forms a PLL circuit as explained below. The output stage of the VCO 7 includes a frequency dividing circuit, and in addition to the signal fL output as a reference carrier wave, a signal f which is 90' in phase with respect to this signal fL is generated.
L+906 is taken out. FIG. 2 shows the relationship between the signal fL output from the VCO 7 and fL+90°.

In this figure, the PLL described below is locked, and the output of the input modulated wave f1n and the VCO 7 and the phase O0 of C71fL are shown in a state in which they almost match. The signal fL in this state is the base i1j carrier wave.

The output signal f L + 90° of the VCO 7 is applied to the reset input R of the flip-flop 2 and the other flip-flop 3, and the 7-lip 7θ blocks 2 and 3 are forcibly reset by the signal f L + 900 (1111+).

As is clear from the relationship between the signals fL and fL+90°, the period in which the signal fL+900 is '1'' is the period from 190° to +900 in phase of the signal fL.

The flip-flop 2 receives the pulse signal Δf from the edge detection circuit 1 while the signal fL+90° is 0''.
In response to the in, the signal fL+900 becomes 1" and is reset. Therefore, the output QA of the flip-flop 2 contains the input modulated wave f111 as shown in FIG.
The pulse signal Δ corresponding to the phase O0 or 1800 points of
A pulse is generated that rises in response to fm<small circle in the figure) and falls in response to the rise of signal fL+90°.

When the input modulated wave is inverted from the 00 phase to the 1800 phase and the pulse signal Δfin is missing (indicated by the small dotted circle in the figure), the pulse of the output Q^ of the flip-flop 2 is missing.

The output signal fL of CO7 is applied to the T input of the other flip-flop 3. As a result, similarly to the explanation of light, a pulse signal is generated at the output Qa of the flip-flop 3, which rises in response to the rise of the signal fL and falls in response to the rise of the signal fL+90''.

The output OA of the flip-flop 2 and the output Qa of the flip-flop 3 are inputted to the EOR gate t-4 and their phases are compared. The output signal C of the EOR gate 4 has a signal Q^ as shown in FIG. A pulse with a width equal to the rise timing difference of B is generated. If the pulse of the signal OQB is lost as described above, the pulse of the signal OQB is
This becomes the output signal C of the EOR gate 4.

The output signal C of the FOR gate 4 becomes a control signal for the analog switch 5. A signal obtained by inverting the output signal fL of the VCO 7 with an inverter 8 is input to the analog switch 5, and the output of the analog switch 5 is a control voltage generation circuit. It is input to the integrating circuit 6.

In other words, the signals Q^ and Q that are 1-neared from the EOR gate 4
By adding the logic of the output signal DfL of vCO7 to the signal A corresponding to the time difference between the rise and F of B, the signals SQA and Q
You can see the direction of advance and lag of B and its magnitude. A signal whose lead or lag direction is expressed by a positive or negative voltage and whose magnitude is expressed by a pulse width becomes an integral input to the integrating circuit 6. In the integrating circuit 6, the integrated input is averaged to obtain an integrated output, and this output is used as a control signal for the VCO 7.

In this way, the edge detection circuit 1. Flip-flops 2 and 3. EOR gate 4. The analog switch 5d5, inverter 8, etc. constitute a phase comparison circuit, and the integration circuit 6 and VC07'c constitute a PLL circuit.

What is important here is that flip-flops 2 and 3 are connected to VC
Since the forced reset is performed using the signal jMfL + 90° which is 90' in phase with respect to the reference carrier fL taken out from O7, the phase comparison operation is not performed when the signal Q f L ± 900 is II 1 II. , signal fL+90
The phase comparison operation performed when 0 is "O'" is performed on either the rising or falling edge of the input modulated wave f zn.

Therefore, the input modulated wave f in is changed from 00 phase to 180 phase
When the phase is reversed, a phase difference signal harmful to obtaining a stable reference carrier wave is output from the FOR gate 4, but this occurs only once when the phase of the signal f In is reversed, and the harmful phase difference The pulse width of signal 0 is 1/ of the period of signal F fL.
It is 4. Therefore, the influence on the integrating circuit 6 is very small, and the disturbance of the reference carrier wave fL output from the VCO 7 is also very small.

In addition, after the signal f 1n is inverted, the previous phase comparison was performed on the rising edge of the signal f in.
On the other hand, the phase comparison is performed on the falling edge of the signal fin, and the PLL circuit maintains the locked state without causing almost any disturbance to the reference carrier wave fL.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a reference carrier regeneration circuit according to an embodiment of the present invention, and FIG. 2 is a time chart showing operating waveforms of each part in FIG. 1. 1...Edge detection circuit 2.3...Flip 1] Butt 4...E OR gate 5...Analog switch 6.・・・・・・
...Integrator circuit 7...vCO 8...Inverter patent applicant Tateishi Electric Co., Ltd.

Claims (1)

[Claims] (1) A PLL circuit consisting of a phase comparison circuit, a control voltage generation circuit, and a VCO processes a two-phase PSK modulated wave,
The reference carrier wave is obtained from the VCo, and the phase comparator circuit detects the phase -
It includes comparison period limiting means that performs a comparison operation only in the interval from 90' to 90', and detects the rising and falling edges of the input modulated wave during the limited period by this means, and detects the output signal of the vCO. The circuit is configured to perform a timing comparison with a point of phase o0 of and generate a positive or negative integral input signal according to the timing difference, and the control voltage generating circuit is comprised of an integrating circuit that receives the integral input; A reference carrier regeneration circuit for a two-phase PSK demodulator, which is configured to control the vCO with its integral output.