JPS6362918B2 - - Google Patents

Info

Publication number
JPS6362918B2
JPS6362918B2 JP56184894A JP18489481A JPS6362918B2 JP S6362918 B2 JPS6362918 B2 JP S6362918B2 JP 56184894 A JP56184894 A JP 56184894A JP 18489481 A JP18489481 A JP 18489481A JP S6362918 B2 JPS6362918 B2 JP S6362918B2
Authority
JP
Japan
Prior art keywords
film substrate
film
etching
pattern
foil
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56184894A
Other languages
Japanese (ja)
Other versions
JPS5885590A (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP56184894A priority Critical patent/JPS5885590A/en
Publication of JPS5885590A publication Critical patent/JPS5885590A/en
Publication of JPS6362918B2 publication Critical patent/JPS6362918B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Insulated Metal Substrates For Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)

Description

【発明の詳細な説明】 本発明はフイルム基板構造に関する。[Detailed description of the invention] The present invention relates to film substrate structures.

従来のフイルム基板構造として良く知られてい
るものは第1図に示す如く、ポリイミド、ポリア
シドイミド等の耐熱性プラスチツク層1の両面に
接着剤2で銅箔3を貼着したものである。斯るフ
イルムリード構造はフレキシブル回路基板として
多くの電子機器の回路基板として用いられ、フイ
ルムキヤリア方式による量産性を最大の特徴とし
ている。
A well-known conventional film substrate structure, as shown in FIG. 1, is one in which copper foil 3 is adhered to both sides of a heat-resistant plastic layer 1 made of polyimide, polyacidoimide, etc. with an adhesive 2. Such a film lead structure is used as a flexible circuit board for many electronic devices, and its greatest feature is mass production using the film carrier method.

しかしながら斯るポリイミド等を用いたフイル
ム基板構造が一般に普及しないのは、銅箔3の支
持するポリイミド等のプラスチツク層1がきわめ
て高価、即ち1m2当り約1万円であるためであ
る。
However, the reason why such a film substrate structure using polyimide or the like is not widely used is that the plastic layer 1 made of polyimide or the like supported by the copper foil 3 is extremely expensive, that is, approximately 10,000 yen per square meter.

本発明は斯点に鑑みてなされ、極めて安価なフ
イルム基板構造を実現することを目的としてい
る。以下に第2図および第5図を参照して本発明
の一実施例を詳述する。
The present invention was made in view of this point, and an object of the present invention is to realize an extremely inexpensive film substrate structure. An embodiment of the present invention will be described in detail below with reference to FIGS. 2 and 5.

本発明に依るフイルム基板構造は第2図に示す
如く、二枚の銅箔11,12を支持用金属箔13
の両面に熱硬化性樹脂の接着剤14で接着して形
成される。二枚の銅箔11,12はプリント基板
等に用いられる約35μ厚の銅箔を用い、銅箔1
1,12の片面には一面にエポキシ樹脂等の熱硬
化性樹脂から成る接着剤14を塗布した後に支持
用金属箔13の両面に圧着して一体化してフイル
ム状にする。熱硬化性樹脂としては例えば特公昭
55−20394号公報に記載したものを用いると良い。
支持用金属箔13としては50〜100μ厚のアルミ
ニウム箔が安価で適当であるが、銅箔を用いても
良い。二枚の銅箔11,12および支持用金属箔
13は互いに約15〜30μ厚の接着剤14で電気的
に絶縁され、最低でも600V、平均では2500Vの
絶縁耐圧が得られる。しかし接着剤14は極めて
薄層であるので、プレス切断をすると切断面で接
着剤14の薄層が破れて短絡する危険がある。
The film substrate structure according to the present invention, as shown in FIG.
It is formed by adhering it to both sides with a thermosetting resin adhesive 14. The two copper foils 11 and 12 are approximately 35 μ thick copper foil used for printed circuit boards, etc., and the copper foil 1
An adhesive 14 made of a thermosetting resin such as an epoxy resin is applied to one side of each of the metal foils 1 and 12, and then pressed onto both sides of the supporting metal foil 13 to form a film. Examples of thermosetting resins include Tokkosho
It is preferable to use the one described in Publication No. 55-20394.
As the supporting metal foil 13, aluminum foil with a thickness of 50 to 100 μm is inexpensive and suitable, but copper foil may also be used. The two copper foils 11, 12 and the supporting metal foil 13 are electrically insulated from each other with an adhesive 14 having a thickness of about 15 to 30 μm, and a dielectric strength voltage of at least 600V and on average 2500V is obtained. However, since the adhesive 14 is an extremely thin layer, when press cutting is performed, there is a risk that the thin layer of the adhesive 14 will be torn at the cut surface, resulting in a short circuit.

斯るフイルム基板は所定の巾例えば約5cm巾に
切断して帯状フイルムとして例えば長さ50m単位
にカートリツジに巻き取る。この帯状のフイルム
基板15は第3図に示す如く所望のリードパター
ン16を設けない両端部分に一定間隔でインデツ
クス孔17を打抜いて形成し、このインデツクス
孔17を以後の製造工程での位置の割出しやフイ
ルム基板の移送に用いる。
Such a film substrate is cut into a predetermined width, for example, about 5 cm, and wound into a cartridge in units of, for example, 50 m in length as a strip film. As shown in FIG. 3, this strip-shaped film substrate 15 has index holes 17 punched out at regular intervals on both ends where the desired lead pattern 16 is not provided. Used for indexing and transporting film substrates.

上述したフイルム基板の一方の銅箔11は選択
的にエツチングして第3図に示す如く、所望のリ
ードパターン16を形成する。リードパターン1
6は各々が電気的に独立して形成され、具体的に
は半導体素子を載置する固着パツド161とフイ
ルム基板の両端にDIP状に配列された外部端子を
固着する電極162から固着パツド161の近傍
まで延在される各電極リード163より構成され
ている。またリードパターン16はエツチングに
より形成されるため不所望の力が加えられず接着
剤14の薄層を破つて短絡することはない。また
リードパターン16はインデツクス孔17により
割り出される位置に一方の銅箔11を用いて一定
間隔で同一のものを連続的に形成してフイルムキ
ヤリア方式の生産工程に適応させる。
The copper foil 11 on one side of the film substrate described above is selectively etched to form a desired lead pattern 16 as shown in FIG. Lead pattern 1
6 are formed electrically independently, and specifically, from the fixing pad 161 on which the semiconductor element is mounted and the electrodes 162 fixing the external terminals arranged in a DIP shape on both ends of the film substrate, to the fixing pad 161. It is composed of each electrode lead 163 extending to the vicinity. Further, since the lead pattern 16 is formed by etching, no undesirable force is applied to the lead pattern 16, thereby preventing the thin layer of the adhesive 14 from breaking and causing a short circuit. Further, the same lead pattern 16 is continuously formed at regular intervals using one of the copper foils 11 at the position determined by the index hole 17, thereby adapting to the film carrier type production process.

またフイルム基板の他方の銅箔12は第4図に
示す如く固着パツド161に対応する部分に固着
パターン20を設ける。なお多層配線を行う必要
がある場合は、他方の銅箔12を用いて導電路2
1を形成し、反対側のリードパターン16とスル
ホール接続する。固着パターン20および導電路
21はリードパターン16と同様にエツチングに
より形成される。
Further, the other copper foil 12 of the film substrate is provided with a fixing pattern 20 at a portion corresponding to the fixing pad 161, as shown in FIG. Note that if it is necessary to perform multilayer wiring, use the other copper foil 12 to connect the conductive path 2.
1 is formed and connected to the lead pattern 16 on the opposite side through-hole. The fixed pattern 20 and the conductive path 21 are formed by etching similarly to the lead pattern 16.

斯るフイルム基板の二枚の銅箔11,12のエ
ツチングは両面に所望の形状にレジストをスクリ
ーン印刷した後に両面エツチング装置内にフイル
ム基板を連続して送り込み、エツチング液を対向
して設けたノズルから両面に吹き付けて同時にエ
ツチングを行う。
Etching of the two copper foils 11 and 12 on such a film substrate is carried out by screen printing a resist in the desired shape on both sides, and then continuously feeding the film substrate into a double-sided etching device, and applying the etching liquid through nozzles arranged opposite to each other. Spray on both sides and perform etching at the same time.

上述の如く両面エツチングにより所定のリード
パターン16および裏面パターンを形成されたフ
イルム基板はカートリツジに巻き取られ、その後
カートリツジからインデツクス孔17を用いてコ
マ送りして供給され、第5図に示す如く固着パツ
ド161に半導体素子22等を固着し半導体素子
22の電極と対応する電極リード163とをボン
デイング細線で接続する。一方固着パターン20
にはクリーム状半田をスクリーン印刷した後放熱
のための良熱伝導性の金属片23を固着する。
The film substrate on which the predetermined lead pattern 16 and back surface pattern have been formed by double-sided etching as described above is wound up into a cartridge, and then fed frame by frame from the cartridge using the index hole 17, and fixed as shown in FIG. The semiconductor element 22 and the like are fixed to the pad 161, and the electrodes of the semiconductor element 22 and the corresponding electrode leads 163 are connected with bonding thin wires. On the other hand, fixed pattern 20
After screen printing creamy solder, a metal piece 23 with good thermal conductivity for heat radiation is fixed.

この際に電極リード163に通電して半導体素
子22および他の回路素子を含めた全体の回路機
能検査を行い、必要があればフアンクシヨナルト
リミングも行える。この検査で所定の回路機能を
得られないときは半導体素子22等を交換して再
生するか、あるいはマークを付けてその後の組立
工程を中止して完成品の歩留の向上を図る。この
検査後半導体素子22および保護を必要とする回
路素子にはシリコンレンジ塗布して素子およびボ
ンデイング細線を保護する。
At this time, the electrode lead 163 is energized to inspect the overall circuit function including the semiconductor element 22 and other circuit elements, and functional trimming can be performed if necessary. If a predetermined circuit function cannot be obtained through this inspection, the semiconductor element 22 or the like is replaced and remanufactured, or a mark is attached and the subsequent assembly process is stopped to improve the yield of the finished product. After this inspection, the semiconductor element 22 and circuit elements requiring protection are coated with silicone in a microwave oven to protect the elements and bonding thin wires.

その後フイルム状のままで電極リード163の
他端に外部端子24を半田付けした後、外部端子
24を露出して全体を樹脂でモールドし、然る後
封止樹脂25の端部でフイルム基板15を切断し
て第5図に示す個々の完成品に分離する。
After that, the external terminal 24 is soldered to the other end of the electrode lead 163 while still in the film form, and then the external terminal 24 is exposed and molded entirely with resin. are cut and separated into individual finished products as shown in FIG.

以上に詳述した如く本発明に依れば、二枚の銅
箔と一枚の支持用金属箔によつて極めて安価で放
熱性の良いフイルム基板構造が実現でき、また銅
箔でリードパターンを多数連続して形成すること
によりフイルムキヤリア方式を適用して量産性を
得られる。更に従来では不可能とされた電力消費
の大きい回路についてもフイルムキヤリア方式を
適用でき、電力消費量に応じた金属片により良好
な放熱性も確保できる。
As detailed above, according to the present invention, an extremely inexpensive film board structure with good heat dissipation can be realized by using two copper foils and one support metal foil, and the lead pattern can be formed using copper foil. By forming a large number of them in succession, mass production can be achieved by applying the film carrier method. Furthermore, the film carrier method can be applied to circuits with high power consumption, which was considered impossible in the past, and good heat dissipation can be ensured by using metal pieces according to the power consumption.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のポリイミド等の耐熱性プラスチ
ツク層を用いたフイルム基板構造を説明する断面
図、第2図は本発明のフイルム基板構造を示す断
面図、第3図および第4図は本発明のフイルム基
板を用いた半導体装置の組立方法を説明する上面
図、第5図は本発明のフイルム基板を用いた半導
体装置の断面図である。 主な図番の説明 11,12は銅箔、13は支
持用金属箔、14は接着剤層、15はフイルム基
板、16はリードパターン、17はインデツクス
孔、22は半導体素子、23は金属片、24は外
部端子である。
FIG. 1 is a sectional view illustrating a conventional film substrate structure using a heat-resistant plastic layer such as polyimide, FIG. 2 is a sectional view showing a film substrate structure according to the present invention, and FIGS. 3 and 4 are illustrative of the present invention. FIG. 5 is a top view illustrating a method of assembling a semiconductor device using the film substrate of the present invention, and FIG. 5 is a sectional view of the semiconductor device using the film substrate of the present invention. Explanation of main drawing numbers 11 and 12 are copper foils, 13 is supporting metal foil, 14 is adhesive layer, 15 is film substrate, 16 is lead pattern, 17 is index hole, 22 is semiconductor element, 23 is metal piece , 24 are external terminals.

Claims (1)

【特許請求の範囲】[Claims] 1 二枚の銅箔が熱硬化性樹脂で支持用金属箔の
両面に接着して形成されたフイルム基板と、前記
フイルム基板の一方の銅箔をエツチングして一定
間隔で形成され少なくとも半導体素子が固着され
る固着パツドを有する導電パターンと、前記フイ
ルム基板の他の銅箔をエツチングし前記固着パツ
ドに対応して形成された多層配線用の導電路及び
放熱用の金属片が固着される固着パターンとを備
えたことを特徴とするフイルム基板構造。
1 A film substrate formed by adhering two copper foils to both sides of a supporting metal foil with a thermosetting resin, and etching one of the copper foils of the film substrate to form etchings at regular intervals, and at least semiconductor elements are formed on the film substrate. A conductive pattern having a fixing pad to be fixed, and a fixing pattern to which a conductive path for multilayer wiring and a metal piece for heat dissipation are fixed, which are formed by etching another copper foil of the film substrate and corresponding to the fixing pad. A film substrate structure characterized by comprising:
JP56184894A 1981-11-17 1981-11-17 Film substrate structure Granted JPS5885590A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56184894A JPS5885590A (en) 1981-11-17 1981-11-17 Film substrate structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56184894A JPS5885590A (en) 1981-11-17 1981-11-17 Film substrate structure

Publications (2)

Publication Number Publication Date
JPS5885590A JPS5885590A (en) 1983-05-21
JPS6362918B2 true JPS6362918B2 (en) 1988-12-05

Family

ID=16161175

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56184894A Granted JPS5885590A (en) 1981-11-17 1981-11-17 Film substrate structure

Country Status (1)

Country Link
JP (1) JPS5885590A (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS513376A (en) * 1974-06-29 1976-01-12 Ebara Infilco
JPS51145857A (en) * 1975-06-11 1976-12-15 Citizen Watch Co Ltd Timekeeper substrate
JPS558777A (en) * 1978-07-06 1980-01-22 Terada Keori Kk Preparation of lap blanket
JPS5553477A (en) * 1978-10-13 1980-04-18 Matsushita Electric Ind Co Ltd Electronic circuit device and method of manufacturing same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS513376A (en) * 1974-06-29 1976-01-12 Ebara Infilco
JPS51145857A (en) * 1975-06-11 1976-12-15 Citizen Watch Co Ltd Timekeeper substrate
JPS558777A (en) * 1978-07-06 1980-01-22 Terada Keori Kk Preparation of lap blanket
JPS5553477A (en) * 1978-10-13 1980-04-18 Matsushita Electric Ind Co Ltd Electronic circuit device and method of manufacturing same

Also Published As

Publication number Publication date
JPS5885590A (en) 1983-05-21

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