JPS5885590A - Film substrate structure - Google Patents
Film substrate structureInfo
- Publication number
- JPS5885590A JPS5885590A JP56184894A JP18489481A JPS5885590A JP S5885590 A JPS5885590 A JP S5885590A JP 56184894 A JP56184894 A JP 56184894A JP 18489481 A JP18489481 A JP 18489481A JP S5885590 A JPS5885590 A JP S5885590A
- Authority
- JP
- Japan
- Prior art keywords
- film substrate
- substrate structure
- film
- copper foil
- foil
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Insulated Metal Substrates For Printed Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】 本発明はフィルム基板構造に関する。[Detailed description of the invention] FIELD OF THE INVENTION The present invention relates to film substrate structures.
従来のフィルム基板構造として良く知られているものは
第1図≦二示す如く、ポリイミド,ポリアシドイミド等
の耐熱性プラスチック層(1)の両面に接着剤(2)で
銅箔+31を貼着したものである.、貼るフイルムリー
ト゜構aはフレキシブル回路基板として多くの電子張器
の回路基板として用いられ.フィルムキャリア方式《二
よる晴産性を最大の特徴としている。A well-known conventional film substrate structure is one in which copper foil +31 is attached with adhesive (2) to both sides of a heat-resistant plastic layer (1) made of polyimide, polyacidoimide, etc., as shown in Figure 1≦2. It is. The film strip structure a is used as a flexible circuit board for many electronic tensioners. Film carrier method《The biggest feature is the two-way success rate.
しかしながら断るポリイミド゛等を用いたフィルム基板
構造が一般に普績しrcいのは一銅箔131の交将をす
るポリイミド等のプラスチック層(1)がきわめて高価
,μDち1m2当り約1万円であるためである。However, the film substrate structure using polyimide etc. is generally popular because the plastic layer (1) made of polyimide etc. that intersects the copper foil 131 is extremely expensive, costing about 10,000 yen per 1 m2 of μD. This is because there is.
本発明は断点《1檻みてなされ.lIi!みて安価なフ
ィルム基板構造を実現することを目的としている。The present invention was made with a view to the point of view. lIi! The aim is to realize an inexpensive film substrate structure.
以−ドに弟2図および弟5図を参照して本発明の一実施
例を詳述する。Hereinafter, one embodiment of the present invention will be described in detail with reference to the younger brother 2 and the younger 5 figures.
本発明(1依るフィルム基板構造は弟2図に示す如く、
二枚の銅箔(111fl2を文持用金回箔03の両■に
熱硬化性制帽の接着剤[141で接着して形成される。The film substrate structure according to the present invention (1) is as shown in Fig. 2,
It is formed by adhering two pieces of copper foil (111fl2) to both sides of gold leaf 03 for holding a pattern using a thermosetting cap adhesive [141].
二枚の銅箔IDG3はプリント基板等に用いられる約3
5μ厚の銅箔を用い、銅箔(111拐の片面には一面に
エポキシ樹脂等の熱を更化性樹指から成る接着剤Q4]
を塗布した後に交将用金梢箔G3の両面にlf着して一
体化してフィルム状C二するう熱硬化性崩指としては例
えば特公昭55−20394号公報に記載したものを用
いると艮い。文書用金瞑箔(13としては50〜100
μ厚のアルミニウム箔が安価で適当であるが、銅箔を用
いても良い。二枚の銅箔Q11GZおよび文書用金属箔
(13は互いl1約15〜30μ厚の接着剤(14Jで
電気的に絶縁され、最低でも600V、平均では250
DVの絶縁耐Iモが鵡られる。しかし接着剤圓は曜め
てR層であるので、プレス切断をすると切断向で接着剤
f141の薄層が破れて短絡する危険がある。The two copper foils IDG3 are approximately 3cm thick, which is used for printed circuit boards, etc.
Use a copper foil with a thickness of 5 μm, and apply adhesive Q4 made of heat-curable resin such as epoxy resin on one side of the copper foil (111-thickness).
For example, as a thermosetting material, the one described in Japanese Patent Publication No. 55-20394 can be used. stomach. Gold foil for documents (13 is 50-100
Although μ-thick aluminum foil is inexpensive and suitable, copper foil may also be used. Two pieces of copper foil Q11GZ and document metal foil (13 are electrically insulated from each other by l1 about 15-30μ thick adhesive (14J, minimum 600V, average 250V)
The insulation resistance of DV is affected. However, since the adhesive circle is an R layer, there is a risk that the thin layer of adhesive f141 will be torn in the cutting direction when press cutting is performed, resulting in a short circuit.
断るフィルム基板は所定の巾例えば約5儒巾C二切…r
して帯状フィルムとして1111えば長さ5Qm単位に
カートリッジに巻き取る、この帯状のフィルム基板Oe
は第6図に示す如く所望のリードパターン叫を設けない
両端部分に一定聞隔でインデックス孔(171に打抜い
て形成し、このインデックス孔0ηを哨1)動d工程で
の位置の割出しやフィルム基板の移送に用いる、
上述したフィルム基りの一方の銅箔o11は選択的にエ
ツチングして第6図に不一「如< −所望のIJ−トハ
ターン+1dを形成する。リードパターンl]fH1各
々が電気的(二独立して形11にされ、具体的+1;r
半導体素子を載置する固着パッド(ISl)とフィルム
基板の両端にDIP状に配列された外部端子を固着する
電隠(162)から固着バット(161)の近傍まで延
在される各室[IJ−ド(163)より構成されている
。またリードパターンoeはエツチングにより形成され
るため不所望の力が加えられず接着剤041の薄層を破
って短絡することはない。またリードパターンGOハイ
ンデックス孔07)により割り出される位置に一方の銅
箔qllを用いて一定聞隔で151 Lハものを連続
的に形成してフィルムキャリア方式の生産工程に適応さ
せる。The film substrate to be rejected has a predetermined width, for example, approximately 5 mm width C.
This strip-shaped film substrate Oe is then wound onto a cartridge in units of 5 Qm in length as a strip-shaped film.
As shown in Fig. 6, index holes (171) are punched out at regular intervals on both ends where the desired lead pattern is not provided, and the index holes 0η are used as markers 1 to index the position in the moving step. The copper foil o11 on one side of the film base mentioned above, which is used for transporting the film substrate, is selectively etched to form a desired IJ pattern +1d as shown in FIG. fH1 each electrically (two independently shaped 11, concrete +1; r
Each of the chambers [IJ - (163). Further, since the lead pattern oe is formed by etching, no undesired force is applied to the lead pattern oe, so that the thin layer of the adhesive 041 will not be broken and a short circuit will not occur. In addition, one copper foil qll is used at the position determined by the lead pattern GO index hole 07) to continuously form 151 L pieces at constant intervals to adapt to the film carrier type production process.
またフィルム基板の他方の銅箔412は第4図に示Tl
ff1<固着パッド(161)に対応する部分C二固着
パターン(イ)を設ける。なお多層配線を行う必要があ
る場合は、他方の銅箔0を用いて導電路c21)を形成
し7反kr側のリードパターンdQとスルホール接続す
る。固着パターン■および導成略f2Dはリードパター
ンueと同様にエツチングにより形成される。The other copper foil 412 of the film board is shown in FIG.
A part C2 fixing pattern (a) corresponding to ff1<fixing pad (161) is provided. If it is necessary to perform multilayer wiring, a conductive path c21) is formed using the other copper foil 0, and is connected through-hole to the lead pattern dQ on the 7th anti-kr side. The fixed pattern (2) and the conductor f2D are formed by etching in the same way as the lead pattern ue.
断るフィルム基板の二枚の銅箔fll103のエツチン
グは両面(二所望の形状にレジストをスクリーン印刷し
た後にr@血エツチング装置内(ニフィルム基板を1牛
続して送り込み、エツチング酸を対向して設けたノズル
から両面に吹き付けて同時にエツチングを行うう
上述の如く両面エツチングにより所定のリードパターン
0Qおよび一3%lIT]パターンを形成されたフィル
ム基板はカートリッジシニ巻き取られ%七の後カートリ
ッジからインデックス孔Gηを用いてコマ送りして供給
され、第5図に示す如く固着パッド(161)c半導体
素子の等を固着し半導体素子+nの41量と対応する磁
極リード(163)とをボンディング細線で接続する。Etching of the two copper foils (Fll103) of the film substrate was carried out on both sides (after screen printing the resist in the desired shape, the two film substrates were fed into the blood etching device one after another, and the etching acid was applied on opposite sides). The film substrate, on which the predetermined lead patterns 0Q and 13%IT] have been formed by etching both sides at the same time by spraying from a provided nozzle, is wound up into a cartridge and then indexed from the cartridge. It is supplied frame by frame using the hole Gη, and as shown in FIG. 5, the fixing pad (161) c is fixed to the semiconductor element, etc., and the semiconductor element + n 41 quantity and the corresponding magnetic pole lead (163) are bonded with a thin bonding wire. Connecting.
一方固着パターン(イ)にはクリーム状半田をスクリー
ン印刷した後放熱のための良熱伝導性の金属片−を固着
する。On the other hand, after screen-printing creamy solder on the fixing pattern (a), a metal piece with good thermal conductivity for heat radiation is fixed.
この際に4版リード(163)に通電して半導体素子器
および他の回路素子を含めた全体の回路機能検査を行い
、必要があればファンクショナルトリミングも行える。At this time, the fourth version lead (163) is energized to inspect the overall circuit function including the semiconductor device and other circuit elements, and if necessary, functional trimming can be performed.
この検査で所定の回路機能を得られないときは半導体素
子器等を交換して再生するか−あるいはマークを付けて
その後の組立工程を中止して完成品の歩留の向上を図ろ
うこの検査後半導体素子のおよび保護を必要とする回路
素子にはシリコンレンジを塗布して素子およびポンディ
ング細線を保護する。If the specified circuit function cannot be obtained through this inspection, the semiconductor device, etc., should be replaced and remanufactured - or a mark may be placed on it and subsequent assembly processes may be discontinued in order to improve the yield of the finished product. After that, a silicon range is applied to the semiconductor device and circuit elements that require protection to protect the device and the bonding wire.
その後フィルム状のままで電1i 11−ド(163)
の他端(二外部端子碗を半田付けした後、外部端子(至
)を露出して全体を1指でモールドし、然る後封1):
d指(至)の端部でフィルム基板09を切断して第5図
に示す個々のボ成品に分離する。Afterwards, leave it in film form and use it as an electric 1i 11-de (163).
The other end (after soldering the two external terminal bowls, expose the external terminal (to) and mold the whole with one finger, then seal 1):
The film substrate 09 is cut at the end of the d finger to separate it into individual components shown in FIG.
以上に詳述した如く本発明に依れば、二枚の銅箔と一枚
の叉将用金属箔によって極めて安価で放熱性の良いフィ
ルム基板構造が実現でき、また銅箔でリードパターンを
多数連続して形成することによりフィルムキャリア方式
を適用して1産牲を得られる。更に従来では不可能とさ
れた″4力消費の大きい回路についてもフィルムキャリ
ア方式を適用でき、電力lIj費けに応じた金属片によ
り良好な放熱性も確保できる。As detailed above, according to the present invention, an extremely inexpensive film board structure with good heat dissipation can be realized using two copper foils and one metal foil for the fork, and a large number of lead patterns can be formed using the copper foil. By forming them continuously, a film carrier method can be applied and productivity can be obtained. Furthermore, the film carrier method can be applied to circuits with high power consumption, which was considered impossible in the past, and good heat dissipation can be ensured by using metal pieces according to the power consumption.
第1図は従来のポリイミド等の耐熱性プラスチック層を
用いたフィルム基板横向を説明する断面図、第2図は本
発明のフィルム基板構造を示す断m1図、第6図および
第4図は本発明のフィルム基板な用いた半導体装置の組
立方法を説明するL面図、第5図は本発明のフィルム基
板を用いた半導体装置の断lI!、1図である。
主な図番の説明
(ID(拐はw4箔、a3は支持用金属箔、(l引ゴ接
揖剤層・(151はフィルム基板、00はリードパター
ン、07Iはインデックス孔、1%は半導体素子、θは
金属片・@は外部端子である。
出願人 三洋電機株式会社外1名4’<0、t。Fig. 1 is a sectional view illustrating the horizontal orientation of a conventional film substrate using a heat-resistant plastic layer such as polyimide, Fig. 2 is a sectional view showing the film substrate structure of the present invention, and Figs. FIG. 5 is a cross-sectional view of a semiconductor device using the film substrate of the present invention. , Figure 1. Explanation of the main drawing numbers (ID: W4 foil, A3 is metal foil for support, (151 is film substrate, 00 is lead pattern, 07I is index hole, 1% is semiconductor Element, θ is a metal piece, @ is an external terminal. Applicant: 1 person other than Sanyo Electric Co., Ltd. 4'<0, t.
Claims (1)
両面シニ接着してフィルム状とし、少くとも一方の銅箔
をエラキングして所望の導電パターンを形成することを
特徴とするフィルム基板構造う(2)特許請求の範囲第
1項に於いて、前記導電パターンを一定聞隔で形成する
ことを特徴とするフィルム基板構造。 {3} 特許請求の範囲第1項《:於いて,他方の銅
箔をエツチングして金属片の固着パターンを形成するこ
とを特徴とするフィルム基板構造。 《4)特許請求の範囲第1項C二於いて一他方の銅箔を
エツチングして多層配線のための導電路を形成すること
を特徴とするフィルム基板構造。(1) Glue two copper foils together using a thermosetting finger to form a film on both sides of gold deer foil, and then roughen at least one of the copper foils to form the desired conductive pattern. Characteristic Film Substrate Structure (2) A film substrate structure according to claim 1, characterized in that the conductive patterns are formed at regular intervals. {3} Claim 1: A film substrate structure characterized in that the other copper foil is etched to form a fixed pattern of metal pieces. (4) A film substrate structure according to claim 1, C2, characterized in that one copper foil on the other is etched to form a conductive path for multilayer wiring.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56184894A JPS5885590A (en) | 1981-11-17 | 1981-11-17 | Film substrate structure |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56184894A JPS5885590A (en) | 1981-11-17 | 1981-11-17 | Film substrate structure |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5885590A true JPS5885590A (en) | 1983-05-21 |
JPS6362918B2 JPS6362918B2 (en) | 1988-12-05 |
Family
ID=16161175
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56184894A Granted JPS5885590A (en) | 1981-11-17 | 1981-11-17 | Film substrate structure |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5885590A (en) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS513376A (en) * | 1974-06-29 | 1976-01-12 | Ebara Infilco | |
JPS51145857A (en) * | 1975-06-11 | 1976-12-15 | Citizen Watch Co Ltd | Timekeeper substrate |
JPS558777A (en) * | 1978-07-06 | 1980-01-22 | Terada Keori Kk | Preparation of lap blanket |
JPS5553477A (en) * | 1978-10-13 | 1980-04-18 | Matsushita Electric Ind Co Ltd | Electronic circuit device and method of manufacturing same |
-
1981
- 1981-11-17 JP JP56184894A patent/JPS5885590A/en active Granted
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS513376A (en) * | 1974-06-29 | 1976-01-12 | Ebara Infilco | |
JPS51145857A (en) * | 1975-06-11 | 1976-12-15 | Citizen Watch Co Ltd | Timekeeper substrate |
JPS558777A (en) * | 1978-07-06 | 1980-01-22 | Terada Keori Kk | Preparation of lap blanket |
JPS5553477A (en) * | 1978-10-13 | 1980-04-18 | Matsushita Electric Ind Co Ltd | Electronic circuit device and method of manufacturing same |
Also Published As
Publication number | Publication date |
---|---|
JPS6362918B2 (en) | 1988-12-05 |
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