JPH0653383A - Manufacture of substrate for mounting semiconductor element - Google Patents

Manufacture of substrate for mounting semiconductor element

Info

Publication number
JPH0653383A
JPH0653383A JP22346992A JP22346992A JPH0653383A JP H0653383 A JPH0653383 A JP H0653383A JP 22346992 A JP22346992 A JP 22346992A JP 22346992 A JP22346992 A JP 22346992A JP H0653383 A JPH0653383 A JP H0653383A
Authority
JP
Japan
Prior art keywords
semiconductor element
conductor layer
base material
metal powder
lead pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP22346992A
Other languages
Japanese (ja)
Other versions
JP2632762B2 (en
Inventor
Toshiya Matsubara
俊也 松原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsui High Tec Inc
Original Assignee
Mitsui High Tec Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsui High Tec Inc filed Critical Mitsui High Tec Inc
Priority to JP22346992A priority Critical patent/JP2632762B2/en
Publication of JPH0653383A publication Critical patent/JPH0653383A/en
Application granted granted Critical
Publication of JP2632762B2 publication Critical patent/JP2632762B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To provide a manufacture of a substrate for mounting a semiconductor element in which a conductor layer formed on the surface and a base material have a strong bonding and a thin thickness can be obtained and a heat dissipation of the semiconductor element can be improved. CONSTITUTION:While forming pilot holes 11 on the side of a thin plate material 10, a rectangular base material 14 surrounded by transparent holes 13 for separation whose internal and external parts are partially connected through a plurality of connecting pieces 12 is formed inside the pilot holes 11, and an insulating adhesive 16 is applied to a specific region on the base material 14, and a metal powder 17 is spread to secure before the adhesive 16 hardens. Next, a plating is performed on the spread metal powder 17 and a conductor layer 18 is formed. Further, after covering the whole with a resist film, a predetermined lead pattern is exposed and developed on the conductor layer 18 by a photolithography, and then the conductor layer 18 is formed on a lead pattern 19 by an etching treatment.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、特定の機能を有する電
子機能素子が搭載される半導体素子搭載用基板の製造方
法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor element mounting substrate on which an electronic functional element having a specific function is mounted.

【0002】[0002]

【従来の技術】従来の半導体装置に使用するリードフレ
ームは、中央部に半導体素子を搭載する素子搭載部と、
該素子搭載部を中心にして放射状に形成した複数のイン
ナーリードと、該インナーリードに接続されるアウター
リードとを有し、前記素子搭載部に半導体素子を搭載し
た後、該半導体素子のパットと前記インナーリードとを
金属ワイヤを介して連結し、外周を樹脂封止していた
が、このようなリードフレームにおいては、最近の半導
体装置の高集積化、多機能化、小型化に伴って以下に説
明するような種々な問題点を生じた。即ち、従来の半導
体装置においては、更に半導体素子の集積度が高くなり
接続の為にインナーリードの数が増した場合、インナー
リードの先端を半導体素子の近くに配置するか、あるい
はインナーリードと半導体素子との間をあけて金属ワイ
ヤの長さを長くして結線することになるが、インナーリ
ードと半導体素子との距離を近づけると、インナーリー
ドの先端を細くする必要があって、加工が難しくなり、
更にはインナーリードと半導体素子との間隔をあけると
金属ワイヤの長さが長くなって、搬送時あるいはモール
ド時に隣合う金属ワイヤの接触によって不測の短絡を生
じる等の問題点があった。そこで、半導体素子搭載部及
びその周囲のインナーリード部分を備える半導体素子搭
載用基板だけを製造する場合には、絶縁樹脂上に貼着し
た金属箔をエッチング加工によってリードパターンを形
成して製造し、組立時にアウターリードと接合して樹脂
封止する半導体装置が提案されていた。
2. Description of the Related Art A lead frame used in a conventional semiconductor device has an element mounting portion for mounting a semiconductor element in a central portion,
A plurality of inner leads radially formed around the element mounting portion and outer leads connected to the inner leads, and after mounting a semiconductor element on the element mounting portion, a pad of the semiconductor element; The inner lead was connected via a metal wire and the outer periphery was resin-sealed. However, in such a lead frame, due to the recent trend toward higher integration, multifunctionality and miniaturization of semiconductor devices, Various problems have arisen as described in. That is, in the conventional semiconductor device, when the degree of integration of the semiconductor element is further increased and the number of inner leads is increased due to the connection, the tips of the inner leads are arranged near the semiconductor element or the inner leads and the semiconductor element are connected to each other. It is necessary to open the space between the element and the metal wire to extend the length of the wire, but if the distance between the inner lead and the semiconductor element is reduced, it is necessary to make the tip of the inner lead thinner, which makes processing difficult. Becomes
Furthermore, if the distance between the inner lead and the semiconductor element is increased, the length of the metal wire becomes longer, and there is a problem that an unexpected short circuit occurs due to contact between adjacent metal wires during transportation or molding. Therefore, in the case of manufacturing only a semiconductor element mounting substrate having a semiconductor element mounting portion and an inner lead portion around the semiconductor element mounting portion, a lead pattern is formed by etching a metal foil adhered on an insulating resin, and then manufactured. There has been proposed a semiconductor device in which an outer lead is joined and resin-sealed at the time of assembly.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、前記半
導体装置においては、絶縁樹脂上に金属箔を貼着した基
材をエッチングすることによって、インナーリード等を
形成しているので、製造工程中に前記金属箔が剥離し易
いという問題点があった。また、前記絶縁樹脂は一定の
厚みを有するので、半導体装置全体が薄型化が困難とな
り、更には半導体素子の熱放散も悪いという問題点があ
った。本発明はかかる事情に鑑みてなされたもので、表
面に形成される導体層と基材との結合が強固で、更には
薄型化も可能で、半導体素子の熱放散も向上できる半導
体素子搭載用基板の製造方法を提供することを目的とす
る。
However, in the above semiconductor device, the inner leads and the like are formed by etching the base material in which the metal foil is adhered on the insulating resin. There is a problem that the metal foil is easily peeled off. Further, since the insulating resin has a certain thickness, it is difficult to reduce the thickness of the semiconductor device as a whole, and the heat dissipation of the semiconductor element is poor. The present invention has been made in view of the above circumstances, and is for mounting a semiconductor element in which the conductor layer formed on the surface and the base material are firmly bonded to each other, can be made thinner, and can also improve the heat dissipation of the semiconductor element. It is an object to provide a method for manufacturing a substrate.

【0004】[0004]

【課題を解決するための手段】前記目的に沿う請求項1
記載の半導体素子搭載用基板の製造方法は、薄板条材の
側部にパイロット孔を形成すると共に、その内部に、複
数の連結片によって内外が部分的に連結された分離用透
孔によって囲まれる四角形の基材を形成し、該基材上の
特定領域に絶縁性のある接着剤を塗布し、該接着剤が未
硬化の内に更に金属粉を散布固着した後、該散布された
金属粉上にめっきを行って導体層を形成し、更に、全体
をレジスト膜で覆った後に、前記導体層上に写真法によ
って所定のリードパターンを露光・現像した後、エッチ
ング処理によって前記導体層をリードパターンに形成す
るようにして構成されている。ここで、前記薄板条材に
は銅板あるいは銅合金板を使用するのが好ましが、他の
金属板であっても本発明は適用される。また、前記金属
粉およびめっきには銅粉および銅めっきを行うのが好ま
しいが、エッチングが可能な金属粉、金属めっき(例え
ば、ニッケル粉、ニッケルめっき)であれば、本発明は
適用される。また、前記連結片にはVノッチを設けるこ
とも可能である。
A method according to the above-mentioned object.
According to the method for manufacturing a semiconductor element mounting substrate described above, a pilot hole is formed in a side portion of a thin strip material, and a pilot hole is formed in the inside thereof, and is surrounded by a separating through hole whose inside and outside are partially connected by a plurality of connecting pieces. A rectangular base material is formed, an insulating adhesive is applied to a specific area on the base material, and a metal powder is further sprayed and fixed inside the adhesive which is uncured, and then the sprayed metal powder. The conductor layer is formed by plating on the conductor layer, and the entire surface is covered with a resist film. Then, a predetermined lead pattern is exposed and developed on the conductor layer by a photographic method, and then the conductor layer is lead by an etching process. It is configured to be formed in a pattern. Here, it is preferable to use a copper plate or a copper alloy plate for the thin strip material, but the present invention can be applied to other metal plates. Further, it is preferable to perform copper powder and copper plating on the metal powder and plating, but the present invention is applicable to any metal powder or metal plating (eg, nickel powder or nickel plating) that can be etched. Further, it is possible to provide a V notch on the connecting piece.

【0005】[0005]

【作用】請求項1記載の半導体素子搭載用基板の製造方
法は、薄板条材の側部にパッロット孔を設け、その内部
に連結片によって一部連結されているが、分離用透孔に
囲まれる四角形の基材を形成し、この上に接着剤を塗布
して、該接着剤が未硬化の内に金属粉を散布固着した
後、めっきを行うようにしているので、基材に強固に金
属粉とめっきによる導体層を形成することができる。次
に、全体をレジスト膜で覆った後、写真法によって所定
のリードパターンを露光・現像し、エッチング処理によ
ってリードパターンを形成するようにしているので、リ
ードパターンの細かい部分を再現することができ、これ
によって半導体に、より近い高い密度のパターンを造る
ことができ、更には作られたリードパターンの剥離が生
じにくいという作用を有する。そして、前記半導体素子
搭載用基板は、金属の薄板条材の中央に半導体素子を搭
載することになるので、半導体素子によって発生する熱
は基材を介して放散される。また、半導体素子の搭載及
びワイヤリングにあっては、前記薄板条材の側面に設け
られたパイロット孔を基準にして、該薄板条材を正確に
位置決めしながら作業が行なえるので、正確なワイヤリ
ングが可能となる。
According to the method of manufacturing a substrate for mounting a semiconductor element according to claim 1, a parrot hole is provided on a side portion of the thin strip material and is partially connected to the inside by a connecting piece, but is surrounded by a separating through hole. A square base material is formed, an adhesive is applied on top of this, and metal powder is sprayed and fixed inside the adhesive, and then plating is performed. A conductor layer can be formed by plating with metal powder. Next, after covering the whole with a resist film, a predetermined lead pattern is exposed and developed by a photographic method, and the lead pattern is formed by an etching process, so that a fine portion of the lead pattern can be reproduced. As a result, it is possible to form a higher-density pattern closer to the semiconductor, and further, it is possible to prevent peeling of the formed lead pattern. Since the semiconductor element mounting substrate has the semiconductor element mounted in the center of the thin metal strip material, the heat generated by the semiconductor element is dissipated through the base material. Further, in mounting and wiring the semiconductor element, since the work can be performed while accurately positioning the thin strip material with reference to the pilot hole provided on the side surface of the thin strip material, accurate wiring can be performed. It will be possible.

【0006】[0006]

【実施例】続いて、添付した図面を参照しつつ、本発明
を具体化した実施例につき説明し、本発明の理解に供す
る。ここに、図1は本発明の一実施例に係る半導体素子
搭載用基板の製造方法の工程を示す平面図、図2は同側
面図、図3は同部分拡大図、図4は本発明の他の実施例
方法によって製造された半導体素子搭載用基板の平面図
である。
Embodiments of the present invention will now be described with reference to the accompanying drawings to provide an understanding of the present invention. 1 is a plan view showing the steps of a method for manufacturing a semiconductor element mounting substrate according to an embodiment of the present invention, FIG. 2 is a side view thereof, FIG. 3 is an enlarged view of the same portion, and FIG. FIG. 7 is a plan view of a semiconductor element mounting substrate manufactured by another embodiment method.

【0007】図1(A)及び図2(A)に示すように、
銅、銅合金からなる薄板条材10に所定のパイロット孔
11を形成すると共に、その内部に複数の連結片12に
よって部分的に接合した分離用透孔13によって囲まれ
る四角形の基材14をプレス加工によって形成する。前
記連結片12の表面及び/又は裏面には後工程で、該基
材14の分離が容易なように、Vノッチ15を同じくプ
レス加工によって形成しておく。
As shown in FIGS. 1 (A) and 2 (A),
A predetermined pilot hole 11 is formed in a thin strip material 10 made of copper or a copper alloy, and a rectangular base material 14 surrounded by a separating through hole 13 partially joined by a plurality of connecting pieces 12 is pressed therein. It is formed by processing. A V notch 15 is also formed on the front surface and / or the back surface of the connecting piece 12 by a press process so that the base material 14 can be easily separated in a later step.

【0008】次に、図1(B)及び図2(B)に示すよ
うに、基材14にその縁部分を残して絶縁性の接着剤を
塗布し、接着剤層16を形成する。この処理はスクリー
ン印刷法によって行う。そして、この接着剤層16が乾
かない内に、図1(B)、図2(C)に示すようにその
やや内側に金属粉の一例である銅粉17を塗布する。こ
の銅粉17の塗布は基材14の上に適当なマスキングを
行って、該銅粉17を吹きつけても良いが、通常は底部
にスクリーンを備えた升内に銅粉17を入れて、これを
前記接着剤層16の上に乗せて、前記スクリーンを通じ
て銅粉17を散布する。これによって銅粉17は接着剤
層16の内部に食い込むので、銅粉17が充分な強度を
有して接着剤層16に固着される。
Next, as shown in FIGS. 1 (B) and 2 (B), an insulating adhesive is applied to the base material 14 leaving the edge portion thereof to form an adhesive layer 16. This process is performed by the screen printing method. Then, while the adhesive layer 16 does not dry, copper powder 17 which is an example of metal powder is applied slightly inside thereof as shown in FIGS. 1 (B) and 2 (C). The copper powder 17 may be applied by appropriately masking the base material 14 and spraying the copper powder 17, but usually, the copper powder 17 is put in a box having a screen at the bottom, This is placed on the adhesive layer 16 and copper powder 17 is sprinkled through the screen. As a result, the copper powder 17 bites into the adhesive layer 16, so that the copper powder 17 has sufficient strength and is fixed to the adhesive layer 16.

【0009】前記接着剤層16が充分に乾いた後、図1
(C)、図2(D)に示すように、他の部分はレジスト
膜でマスキングして、前記銅粉17の上に無電解銅めっ
きを行い、これによって、銅粉17と銅めっき層が一体
となって、前記接着剤層16の上に剥離困難な導体層1
8を形成する。
After the adhesive layer 16 has dried sufficiently, FIG.
As shown in (C) and FIG. 2 (D), other portions are masked with a resist film, and electroless copper plating is performed on the copper powder 17, whereby the copper powder 17 and the copper plating layer are separated. The conductor layer 1 that is difficult to peel off on the adhesive layer 16 as a unit
8 is formed.

【0010】次に全体をレジスト膜で覆った後、前記導
体層18の上にインナーリード19のリードパターンを
露光・現像し、エッチングして、図1(D)、図2
(E)及び図3に示すように、前記接着剤層16の上に
インナーリード19を形成する。この後、中央の素子搭
載部20に絶縁テープを介して所定の半導体素子を固着
し、導電性ワイヤによって所定のワイヤリングを行い、
前記Vノッチ15の部分から該基材14を切離し、前記
インナーリード19と、例えばプレス加工によって形成
されたアウターリードとを、半田、圧着、ワイヤリン
グ、導電性接着剤を用いたボンディング等によって固着
した後、樹脂封止を行って半導体装置が完成する。
Next, after covering the whole with a resist film, the lead pattern of the inner leads 19 is exposed / developed on the conductor layer 18, and is etched to form a pattern as shown in FIGS.
As shown in (E) and FIG. 3, inner leads 19 are formed on the adhesive layer 16. After that, a predetermined semiconductor element is fixed to the central element mounting portion 20 via an insulating tape, and predetermined wiring is performed with a conductive wire,
The base material 14 is separated from the portion of the V notch 15, and the inner lead 19 and the outer lead formed by pressing, for example, are fixed by soldering, pressure bonding, wiring, bonding using a conductive adhesive, or the like. After that, resin sealing is performed to complete the semiconductor device.

【0011】図4には、本発明の他の実施例によって製
造された半導体素子搭載用基板21を示すが、図に示す
ように前記方法によって複数のインナーリード22、2
3が薄板条材24に接着剤層25を介して設けられてい
る。これによって、半導体装置の小型化を図ることがで
きると共に、薄型化を図ることができる。なお、前記実
施例と同一の構成要素については、同一の番号を付して
その説明を省略する。
FIG. 4 shows a semiconductor element mounting substrate 21 manufactured according to another embodiment of the present invention. As shown in FIG.
3 is provided on the thin strip material 24 with an adhesive layer 25 interposed therebetween. This makes it possible to reduce the size of the semiconductor device and reduce the thickness thereof. The same components as those in the above-described embodiment are designated by the same reference numerals and the description thereof will be omitted.

【0012】なお、以上の実施例においては、前記イン
ナーリードの先端部あるいは後端部に、ワイヤリングあ
るいは圧着性の向上の為、貴金属めっきをすることも可
能である。この場合も前記パイロット孔を利用して位置
決めするが可能であるので、正確なめっきを行うことが
できる。更に、インナーリードと同一平面上に設けた電
源用、接地用のバスリードを備えたLOCやCOLタイ
プの半導体装置に用いる半導体素子搭載用基板にも本発
明は適用できる。
In the above embodiment, the front end or the rear end of the inner lead may be plated with a noble metal in order to improve wiring or pressure bonding. Also in this case, since the positioning can be performed using the pilot hole, accurate plating can be performed. Further, the present invention can be applied to a semiconductor element mounting substrate used for a LOC or COL type semiconductor device having a bus lead for power supply and a grounding provided on the same plane as the inner lead.

【0013】[0013]

【発明の効果】本発明に係る半導体素子搭載用基板の製
造方法は、以上の説明からも明らかなように、薄板条材
の上に接着剤層を形成し、その上に金属粉を塗布し、更
にめっきを行って、導体層を形成しているので、該導体
層によって形成されるリードパターンと薄板条材の接着
性が極めて良好である。そして、接着剤層及び導体層を
極めて薄く形成できるので、薄型の半導体装置を構成す
ることが可能である。また、薄板条材が半導体素子の放
熱板として働くので、半導体素子に熱破壊が生じ難いと
いう利点を有する。
As is apparent from the above description, the method of manufacturing a semiconductor element mounting substrate according to the present invention forms an adhesive layer on a thin strip material, and coats metal powder on it. Since the conductor layer is formed by further plating, the adhesion between the lead pattern formed by the conductor layer and the thin strip material is very good. Since the adhesive layer and the conductor layer can be formed extremely thin, it is possible to form a thin semiconductor device. Further, since the thin strip material acts as a heat dissipation plate of the semiconductor element, there is an advantage that the semiconductor element is less likely to be thermally damaged.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例に係る半導体素子搭載用基板
の製造方法の工程を示す平面図である。
FIG. 1 is a plan view showing steps of a method of manufacturing a semiconductor element mounting substrate according to an embodiment of the present invention.

【図2】同側面図である。FIG. 2 is a side view of the same.

【図3】同部分拡大図である。FIG. 3 is an enlarged view of the same portion.

【図4】本発明の他の実施例方法によって製造された半
導体素子搭載用基板の平面図である。
FIG. 4 is a plan view of a semiconductor element mounting substrate manufactured by a method according to another embodiment of the present invention.

【符号の説明】[Explanation of symbols]

10 薄板条材 11 パイロット孔 12 連結片 13 分離用透孔 14 基材 15 Vノッチ 16 接着剤層 17 銅粉 18 導体層 19 インナーリード 20 素子搭載部 21 半導体素子搭載用基板 22 インナーリード 23 インナーリード 24 薄板条材 25 接着剤層 10 Thin Strip Material 11 Pilot Hole 12 Connection Piece 13 Separation Through Hole 14 Base Material 15 V Notch 16 Adhesive Layer 17 Copper Powder 18 Conductor Layer 19 Inner Lead 20 Element Mounting Part 21 Semiconductor Element Mounting Board 22 Inner Lead 23 Inner Lead 24 Thin Strip Material 25 Adhesive Layer

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 薄板条材の側部にパイロット孔を形成す
ると共に、その内部に、複数の連結片によって内外が部
分的に連結された分離用透孔によって囲まれる四角形の
基材を形成し、該基材上の特定領域に絶縁性のある接着
剤を塗布し、該接着剤が未硬化の内に更に金属粉を散布
固着した後、該散布された金属粉上にめっきを行って導
体層を形成し、更に、全体をレジスト膜で覆った後に、
前記導体層上に写真法によって所定のリードパターンを
露光・現像した後、エッチング処理によって前記導体層
をリードパターンに形成することを特徴とする半導体素
子搭載用基板の製造方法。
1. A pilot hole is formed on a side portion of a thin strip material, and a rectangular base material surrounded by a separating through hole whose inside and outside are partially connected by a plurality of connecting pieces is formed inside the pilot hole. , Applying an insulative adhesive to a specific area on the base material, further spraying and fixing metal powder in the uncured adhesive, and then plating on the scattered metal powder to form a conductor After forming a layer and covering the whole with a resist film,
A method of manufacturing a substrate for mounting a semiconductor element, comprising: exposing and developing a predetermined lead pattern on the conductor layer by a photographic method, and then forming the conductor layer into a lead pattern by etching.
JP22346992A 1992-07-29 1992-07-29 Method of manufacturing substrate for mounting semiconductor element Expired - Fee Related JP2632762B2 (en)

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JP22346992A JP2632762B2 (en) 1992-07-29 1992-07-29 Method of manufacturing substrate for mounting semiconductor element

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JPH0653383A true JPH0653383A (en) 1994-02-25
JP2632762B2 JP2632762B2 (en) 1997-07-23

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002334950A (en) * 1994-03-18 2002-11-22 Hitachi Chem Co Ltd Method of manufacturing semiconductor package and semiconductor package
JP2003046055A (en) * 2001-07-31 2003-02-14 Sanyo Electric Co Ltd Planar body, lead frame, and method for manufacturing semiconductor device
US6528164B1 (en) 1999-09-03 2003-03-04 Sumitomo Chemical Company, Limited Process for producing aromatic liquid crystalline polyester and film thereof
US6746897B2 (en) 1994-03-18 2004-06-08 Naoki Fukutomi Fabrication process of semiconductor package and semiconductor package

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002334950A (en) * 1994-03-18 2002-11-22 Hitachi Chem Co Ltd Method of manufacturing semiconductor package and semiconductor package
US6746897B2 (en) 1994-03-18 2004-06-08 Naoki Fukutomi Fabrication process of semiconductor package and semiconductor package
US7187072B2 (en) 1994-03-18 2007-03-06 Hitachi Chemical Company, Ltd. Fabrication process of semiconductor package and semiconductor package
US6528164B1 (en) 1999-09-03 2003-03-04 Sumitomo Chemical Company, Limited Process for producing aromatic liquid crystalline polyester and film thereof
US6656578B2 (en) 1999-09-03 2003-12-02 Sumitomo Chemical Company, Limited Process for producing aromatic liquid crystalline polyester and film thereof
JP2003046055A (en) * 2001-07-31 2003-02-14 Sanyo Electric Co Ltd Planar body, lead frame, and method for manufacturing semiconductor device
JP4663172B2 (en) * 2001-07-31 2011-03-30 三洋電機株式会社 Manufacturing method of semiconductor device

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