JP2684757B2 - Semiconductor device package - Google Patents
Semiconductor device packageInfo
- Publication number
- JP2684757B2 JP2684757B2 JP8861689A JP8861689A JP2684757B2 JP 2684757 B2 JP2684757 B2 JP 2684757B2 JP 8861689 A JP8861689 A JP 8861689A JP 8861689 A JP8861689 A JP 8861689A JP 2684757 B2 JP2684757 B2 JP 2684757B2
- Authority
- JP
- Japan
- Prior art keywords
- aluminum nitride
- polyimide film
- nitride substrate
- semiconductor device
- device package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置パッケージに関し、特に集積回
路パッケージに関する。The present invention relates to a semiconductor device package, and more particularly to an integrated circuit package.
従来の集積回路パッケージはアルミナ（Al2O3）多層
配線基板を用いたものや、プラスチックピングリッドア
レイパッケージが一般的であった。Conventional integrated circuit packages are generally those using an alumina (Al 2 O 3 ) multilayer wiring board and plastic pin grid array packages.
上述した従来のアルミナ基板やプラスチックを用いた
集積回路パッケージでは、これらの材料のもつ熱伝導率
が低く、基板のみからの熱放散が悪いので高出力集積回
路を直接実装することが不可能であった。In the above-mentioned conventional integrated circuit package using an alumina substrate or plastic, the thermal conductivity of these materials is low and the heat dissipation from only the substrate is poor, so it is impossible to directly mount a high-power integrated circuit. It was
本発明の半導体装置パッケージは、窒化アルミニウム
基板の裏面から突き出して設けられた端子ピンと、前記
窒化アルミニウム基板の表面のチップ搭載部を除いて設
けられたポリイミド膜と、前記ポリイミド膜上に設けら
れスルーホールを介して前記端子ピンに接続される導体
層とを有するというものである。The semiconductor device package of the present invention includes a terminal pin protruding from the back surface of an aluminum nitride substrate, a polyimide film provided on the surface of the aluminum nitride substrate excluding a chip mounting portion, and a through film provided on the polyimide film. And a conductor layer connected to the terminal pin through a hole.
次に、本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図は本発明の一実施例の集積回路パッケージの断
面図である。FIG. 1 is a sectional view of an integrated circuit package according to an embodiment of the present invention.
まず、窒化アルミニウム焼結体からなる窒化アルミニ
ウム基板１に貫通穴を設け金属製の端子ピン２をそう入
する。次に窒化アルミニウム基板１の表面にポリイミド
膜３を形成する。ポリイミド膜３の所定の位置には、ス
ルーホールがあけてあり、その部分では端子ピン２の１
部が露出している。このようなポリイミド膜は、次のよ
うな手順で形成される。まず、東レ社製のフォトニース
UR314（商品名）のような、感光性ポリイミド前駆体ワ
ニスを窒化アルミニウム基板１の表面にコーティングす
る。次にガラスマスクを用いて感光性ポリイミド前駆体
ワニスコーティング膜の所定の部分を露光する。露光
後、アルコールを主成分とする所定の現像液で現像する
と、露光していない部分が現像液に溶解し、他の部分が
残り、スルーホールパターンが得られる。次に加熱する
ことによりポリイミド前駆体をイミド化させ、ポリイミ
ド膜を得る。この加熱時に、感光性成分は揮発し、ポリ
イミド膜中には残らない。こうして所定の位置にスルー
ホールを有するポリイミド膜３が形成される。First, a through hole is provided in an aluminum nitride substrate 1 made of an aluminum nitride sintered body, and a metal terminal pin 2 is inserted therein. Next, a polyimide film 3 is formed on the surface of the aluminum nitride substrate 1. A through hole is opened at a predetermined position of the polyimide film 3, and at that portion, one of the terminal pins 2
The part is exposed. Such a polyimide film is formed by the following procedure. First, Toray's Photo Nice
A surface of the aluminum nitride substrate 1 is coated with a photosensitive polyimide precursor varnish such as UR314 (trade name). Next, a predetermined portion of the photosensitive polyimide precursor varnish coating film is exposed using a glass mask. After exposure, when developed with a predetermined developing solution containing alcohol as a main component, the unexposed portion is dissolved in the developing solution, and the other portion remains, and a through-hole pattern is obtained. Then, the polyimide precursor is imidized by heating to obtain a polyimide film. During this heating, the photosensitive component volatilizes and does not remain in the polyimide film. Thus, the polyimide film 3 having the through holes at the predetermined positions is formed.
次に金又は銅の導体層４をエッチング法又は、選択メ
ッキ法で形成する。以上のような工程により本発明の集
積回路パッケージが製作される。Next, the gold or copper conductor layer 4 is formed by an etching method or a selective plating method. The integrated circuit package of the present invention is manufactured by the above steps.
また、第１図には本発明の集積回路パッケージに半導
体チップ５を実装した状態も図示してある。半導体チッ
プ５の端子（ボンディングパッド）と導体層４とをワイ
ヤーボンディング法等の工程で接続する。最終的には半
導体チップ、ボンディング線、導体層を覆って合成樹脂
でコーディングし保護する。なお、半導体チップは窒化
アルミニウム基板表面のチップ搭載部に例えば銀ペース
トのような良熱伝導性接着剤によりダイボンディングさ
れている。Further, FIG. 1 also shows a state in which the semiconductor chip 5 is mounted on the integrated circuit package of the present invention. The terminal (bonding pad) of the semiconductor chip 5 and the conductor layer 4 are connected by a process such as a wire bonding method. Finally, the semiconductor chip, the bonding wire, and the conductor layer are covered and coated with a synthetic resin for protection. The semiconductor chip is die-bonded to the chip mounting portion on the surface of the aluminum nitride substrate with a good heat conductive adhesive such as silver paste.
窒化アルミニウム基板に直接導体層を設けることは密
着性に問題があり実用的ではないが、ポリイミド膜を間
に設けることにより密着性の悪さは回避できる。又、半
導体チップは熱伝導のよい窒化アルミニウム基板にダイ
ボンディングできるので半導体装置の放熱性が改善され
る。Providing the conductor layer directly on the aluminum nitride substrate has a problem in adhesion and is not practical, but by providing a polyimide film between them, poor adhesion can be avoided. Further, since the semiconductor chip can be die-bonded to the aluminum nitride substrate having good thermal conductivity, the heat dissipation of the semiconductor device is improved.
以上説明したように本発明は、窒化アルミニウム基板
上にポリイミド膜を介して導体層を設けることにより、
放熱性のよい窒化アルミニウム基板を本体とする半導体
装置パッケージを実現できるので高出力半導体装置を単
純な構造で実現できるといった効果がある。また、絶縁
層にポリイミド膜を使用しているため、高周波用集積回
路の実装にも有利である。As described above, the present invention provides a conductor layer via a polyimide film on an aluminum nitride substrate,
Since it is possible to realize a semiconductor device package having an aluminum nitride substrate with good heat dissipation as a main body, it is possible to realize a high-power semiconductor device with a simple structure. Further, since a polyimide film is used for the insulating layer, it is advantageous for mounting a high frequency integrated circuit.
第１図は本発明の一実施例の断面図である。 １……窒化アルミニウム基板、２……端子ピン、３……
ポリイミド膜、４……導体層、５……半導体チップ、６
……ボンディング線。FIG. 1 is a sectional view of one embodiment of the present invention. 1 ... Aluminum nitride substrate, 2 ... Terminal pins, 3 ...
Polyimide film, 4 ... Conductor layer, 5 ... Semiconductor chip, 6
...... Bonding wire.
Claims (1)
て設けられた端子ピンと、前記窒化アルミニウム基板の
表面のチップ搭載部を除いて設けられたポリイミド膜
と、前記ポリイミド膜上に設けられスルーホールを介し
て前記端子ピンに接続される導体層とを有することを特
徴とする半導体装置パッケージ。1. A terminal pin projecting from the rear surface of an aluminum nitride substrate, a polyimide film provided on the surface of the aluminum nitride substrate excluding a chip mounting portion, and a through hole provided on the polyimide film. And a conductor layer connected to the terminal pin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8861689A JP2684757B2 (en) | 1989-04-07 | 1989-04-07 | Semiconductor device package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8861689A JP2684757B2 (en) | 1989-04-07 | 1989-04-07 | Semiconductor device package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02267956A JPH02267956A (en) | 1990-11-01 |
| JP2684757B2 true JP2684757B2 (en) | 1997-12-03 |
Family
ID=13947740
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8861689A Expired - Lifetime JP2684757B2 (en) | 1989-04-07 | 1989-04-07 | Semiconductor device package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2684757B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08111587A (en) * | 1994-10-11 | 1996-04-30 | Fujitsu Ltd | Wiring board structure, manufacture thereof, and semiconductor device |
-
1989
- 1989-04-07 JP JP8861689A patent/JP2684757B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02267956A (en) | 1990-11-01 |
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