JPS6256656B2 - - Google Patents
Info
- Publication number
- JPS6256656B2 JPS6256656B2 JP56005672A JP567281A JPS6256656B2 JP S6256656 B2 JPS6256656 B2 JP S6256656B2 JP 56005672 A JP56005672 A JP 56005672A JP 567281 A JP567281 A JP 567281A JP S6256656 B2 JPS6256656 B2 JP S6256656B2
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- copper foil
- film substrate
- lead
- lead pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 36
- 239000011889 copper foil Substances 0.000 claims description 36
- 239000000758 substrate Substances 0.000 claims description 26
- 238000005530 etching Methods 0.000 claims description 9
- 229920005989 resin Polymers 0.000 claims description 7
- 239000011347 resin Substances 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 7
- 229920001187 thermosetting polymer Polymers 0.000 claims description 5
- 239000000853 adhesive Substances 0.000 description 13
- 230000001070 adhesive effect Effects 0.000 description 13
- 239000004642 Polyimide Substances 0.000 description 5
- 229920001721 polyimide Polymers 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000004033 plastic Substances 0.000 description 3
- 229920003023 plastic Polymers 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000002787 reinforcement Effects 0.000 description 2
- 239000004962 Polyamide-imide Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 235000012489 doughnuts Nutrition 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000011990 functional testing Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920002312 polyamide-imide Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49534—Multi-layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49572—Lead-frames or other flat leads consisting of thin flexible metallic tape with or without a film carrier
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/022—Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Description
【発明の詳細な説明】 本発明はフイルム基板構造に関する。[Detailed description of the invention] The present invention relates to film substrate structures.
従来のフイルム基板構造として良く知られてい
るものは第１図に示す如く、ポリイミド、ポリア
ミドイミド等の耐熱性プラスチツク層１上に接着
剤２で銅箔３を貼着したものがある。斯るフイル
ムリード構造はフレキシブル回路基板として多く
の電子機器の回路基板として用いられ、フイルム
キヤリア方式による量産性を最大の特徴してい
る。 A well-known conventional film substrate structure is, as shown in FIG. 1, in which a copper foil 3 is adhered with an adhesive 2 onto a heat-resistant plastic layer 1 made of polyimide, polyamideimide, or the like. Such a film lead structure is used as a flexible circuit board for many electronic devices, and its greatest feature is mass production through the film carrier method.
しかしながら斯るポリイミド等を用いたフイル
ム基板構造が一般に普及しないのは、銅箔３の支
持をするポリイミド等のプラスチツク層１が極め
て高価、即ち１m2当り約10000円であるためであ
る。また多層配線を実現する場合ポリイミド等は
伸縮性を有するので貫通孔を形成し難く、貫通孔
を設けても両面の導体を接続するために必ずスル
ーホールメツキを必要としており多層化にあまり
適していないためである。 However, the reason why such a film substrate structure using polyimide or the like is not widely used is that the plastic layer 1 made of polyimide or the like that supports the copper foil 3 is extremely expensive, that is, approximately 10,000 yen per 1 m 2 . Furthermore, when realizing multilayer wiring, it is difficult to form through holes in materials such as polyimide due to its elasticity, and even if through holes are provided, through hole plating is always required to connect conductors on both sides, making it not suitable for multilayer wiring. This is because there is no
本発明は斯点に鑑みてなされ、極めて安価なフ
イルム基板構造を実現することを目的としてい
る。以下に第２図乃至第８図を参照して本発明の
一実施例を詳述する。 The present invention was made in view of this point, and an object of the present invention is to realize an extremely inexpensive film substrate structure. An embodiment of the present invention will be described in detail below with reference to FIGS. 2 to 8.
本発明に依るフイルム基板構造は第２図に示す
如く、二枚の銅箔１１，１２を互いに熱硬化性樹
脂の接着剤１３で接着して形成される。二枚の銅
箔１１，１２はプリント基板等に用いられる約35
μ厚の銅箔を用い、一方あるいは両方の銅箔１
１，１２の一面にエポキシ樹脂等の熱硬化性樹脂
から成る接着剤１３を塗布した後に圧着しながら
二枚の銅箔１１，１２を一体化してフイルム状に
する。熱硬化性樹脂としては例えば特公昭55−
20394号公報に記載したものを用いる。二枚の銅
箔１１，１２は互いに約15〜30μ厚の接着剤１３
で電気的に絶縁され、最低でも600V平均では
2500Vの絶縁耐圧が得られる。しかし接着剤１３
は極めて薄層であるので、プレス切断をすると切
断面で接着剤１３の薄層が破れて二枚の銅箔１
１，１２はシヨートする危険がある。 As shown in FIG. 2, the film substrate structure according to the present invention is formed by bonding two copper foils 11 and 12 to each other with a thermosetting resin adhesive 13. The two copper foils 11 and 12 are approximately 35 cm thick, which is used for printed circuit boards, etc.
Using μ-thick copper foil, one or both copper foils 1
After applying an adhesive 13 made of a thermosetting resin such as epoxy resin to one side of the copper foils 1 and 12, the two copper foils 11 and 12 are integrated while being pressed together to form a film. As a thermosetting resin, for example,
The one described in Publication No. 20394 is used. The two copper foils 11 and 12 are glued together with an adhesive 13 with a thickness of about 15 to 30μ.
electrically isolated with at least 600V average
A dielectric breakdown voltage of 2500V can be obtained. However, adhesive 13
is an extremely thin layer, so when it is press cut, the thin layer of adhesive 13 is torn at the cut surface and the two sheets of copper foil 1 are separated.
1 and 12 are at risk of being shot.
斯るフイルム基板は所定の巾例えば約５cm巾に
切断して帯状フイルムとして例えば長さ50ｍ単位
にカートリツジに巻き取る。この帯状フイルム基
板には第３図の如く所望のリードパターンを設け
ない両端部分に一定間隔でインデツクス孔１５を
打抜いて形成し、このインデツクス孔１５を以後
の製造工程での位置の割出しやフイルム基板の送
りに用いる。 Such a film substrate is cut into a predetermined width, for example, about 5 cm, and wound into a cartridge in units of, for example, 50 m in length as a strip film. As shown in FIG. 3, index holes 15 are punched out at regular intervals on both ends of the strip-shaped film substrate where no desired lead pattern is provided. Used for feeding film substrates.
上述したフイルム基板の一方の銅箔１１は選択
的にエツチングして第３図に示す如く、所望のリ
ードパターン１６と両端にインデツクス孔１５を
含んで連なる帯状パターン１７を形成する。帯状
パターン１７はフイルム基板１４を送るときに加
わる力からリードパターン１６を保護するための
ものである。更に十分にリードパターン１６を保
護するためには帯状パターン１７をはしご状に接
続する連結パターン１８を設け、帯状パターン１
７と連結パターン１８で完全にリードパターン１
６を囲む。リードパターン１６は各々が電気的に
独立し且つ帯状パターン１７および連結パターン
１８と電気的に独立させておく。リードパターン
１６は具体的には半導体素子を載置する固着パツ
ド１６１とフイルム基板の両端にデユアル・イ
ン・ライン状に配列された外部端子を固着する電
極１６２から固着パツド１６１の近傍まで延在さ
れる各電極リード１６３より構成されている。ま
たリードパターン１６はエツチングにより形成す
るため不所望な力が加えられず接着剤１３の薄層
を破つて短絡することはない。またリードパター
ン１６はインデツクス孔１５により割り出される
位置に一方の銅箔１１を用いて一定間隔で同一の
ものを連続的に形成してフイルムキヤリア方式の
生産工程に適応させる。 The copper foil 11 on one side of the film substrate described above is selectively etched to form a strip pattern 17 which is connected to a desired lead pattern 16 and includes index holes 15 at both ends, as shown in FIG. The strip pattern 17 is for protecting the lead pattern 16 from the force applied when the film substrate 14 is fed. In order to further sufficiently protect the lead pattern 16, a connecting pattern 18 is provided to connect the strip patterns 17 in a ladder shape.
Completely lead pattern 1 with 7 and connected pattern 18
Surround 6. Each of the lead patterns 16 is electrically independent and electrically independent of the strip pattern 17 and the connection pattern 18. Specifically, the lead pattern 16 extends from the fixing pad 161 on which the semiconductor element is placed and the electrodes 162 fixing the external terminals arranged in a dual-in-line manner at both ends of the film substrate to the vicinity of the fixing pad 161. The electrode lead 163 is composed of each electrode lead 163. Further, since the lead pattern 16 is formed by etching, no undesirable force is applied, and the thin layer of the adhesive 13 is not broken and short circuits occur. Further, the same lead pattern 16 is continuously formed at regular intervals using one of the copper foils 11 at the position determined by the index hole 15, thereby adapting to the film carrier type production process.
またフイルム基板の他方の銅箔１２は図示しな
いが全部残してリードパターン１６の支持をさせ
る。各リードパターン１６は接着剤１３を介して
他方の銅箔１２と接着されているので、各リード
パターン１６の引張り強度は一枚の銅箔と全く同
じである。この結果強度的には一枚の銅箔と同様
に取扱いができ、フイルムキヤリア生産方式を採
用することができる。しかし斯上の構造では他方
の銅箔１２とリードパターン１６間に寄生容量が
発生するために高周波回路に適さない。そこで第
４図および第５図に示す様に他方の銅箔１２を選
択的にエツチング除去して寄生容量を減少させ
る。第４図に於いて、点線は一方の銅箔１１面の
リードパターン１６、帯状パターン１７等を示し
ており、反対側の銅箔１２は固着パツド１６１と
固着パツド１６１に近接したボンデイングを行う
電極リード１６３の一端と外部端子を接続する電
極リード１６２の他端に対応する部分および帯状
パターン１７と連結パターン１８に対応する部分
を残してドーナツ状にエツチング除去する。第５
図は帯状パターン１７と連結パターン１８に対応
する部分を残してリードパターン１６を形成する
領域を斜ストライプ状にエツチング除去したもの
である。この様に他方の銅箔１２のエツチング形
状は一方の銅箔１１面に形成されるリードパター
ン１６の形状に対応して決定され、半導体素子、
チツプ部品、外部端子等を固着する部分は補強の
ため残しておく必要がある。また補強を必要とし
ないリードパターン１６部分は接着剤１３の薄層
でほとんど支持できないので、他方の銅箔１２を
残しておき少くとも一個所で接着剤１３を介して
重畳させておく必要がある。 Further, although not shown, the other copper foil 12 of the film substrate is left in its entirety to support the lead pattern 16. Since each lead pattern 16 is bonded to the other copper foil 12 via the adhesive 13, the tensile strength of each lead pattern 16 is exactly the same as that of a single sheet of copper foil. As a result, it can be handled in the same way as a single sheet of copper foil in terms of strength, and a film carrier production method can be adopted. However, the above structure is not suitable for high frequency circuits because parasitic capacitance occurs between the other copper foil 12 and the lead pattern 16. Therefore, as shown in FIGS. 4 and 5, the other copper foil 12 is selectively etched away to reduce the parasitic capacitance. In FIG. 4, dotted lines indicate the lead pattern 16, strip pattern 17, etc. on one side of the copper foil 11, and the copper foil 12 on the opposite side indicates the fixing pad 161 and the electrode to be bonded close to the fixing pad 161. Etching is performed in a donut shape, leaving a portion corresponding to the other end of the electrode lead 162 connecting one end of the lead 163 and an external terminal, and a portion corresponding to the strip pattern 17 and the connection pattern 18. Fifth
The figure shows a region in which a lead pattern 16 will be formed, leaving a portion corresponding to a strip pattern 17 and a connecting pattern 18, etched away in a diagonal stripe pattern. In this way, the etching shape of the other copper foil 12 is determined in accordance with the shape of the lead pattern 16 formed on one side of the copper foil 11, and
It is necessary to leave the parts to which chip parts, external terminals, etc. are fixed for reinforcement purposes. Also, since the part of the lead pattern 16 that does not require reinforcement can hardly be supported by the thin layer of adhesive 13, it is necessary to leave the other copper foil 12 and overlap it at least in one place with the adhesive 13 interposed therebetween. .
斯るフイルム基板の二枚の銅箔１１，１２のエ
ツチングは両面に所望形状のレジストをスクリー
ル印刷した後に両面エツチング装置内にフイルム
基板を連続して送り込み、エツチング液を対向し
て設けたノズルから両面に吹き付けて同時にエツ
チングを行う。 Etching of the two copper foils 11 and 12 of such a film substrate is carried out by screel printing a resist of a desired shape on both sides, then feeding the film substrate continuously into a double-sided etching device, and applying an etching liquid from nozzles arranged opposite to each other. Spray on both sides and etch at the same time.
上述の如く両面エツチングにより所定のリード
パターン１６および裏面パターンを形成されたフ
イルム基板はカートリツジに巻き取り収納され、
その後カートリツジからインデツクス孔１５を用
いてコマ送りして供給され第６図に示す様に固着
パツド１６１に半導体素子２０等を固着し半導体
素子２０の電極と対応する電極リード１６３とを
ボンデイング細線で接続した後、電極リード１６
３に通電して半導体素子２０および他の回路素子
を含めた全体の回路機能検査を行い必要であれば
フアンクシヨナルトリミングも行う。この検査で
所定の回路機能を得られないときは半導体素子２
０等を交換して再生するか、あるいはマークを付
けてその後の組立工程を中止して完成品の歩留の
向上を図る。この検査後半導体素子２０および保
護を必要とする回路素子にはシリコンレジンを塗
布して素子およびボンデイング細線を保護する。 The film substrate on which the predetermined lead pattern 16 and back pattern have been formed by double-sided etching as described above is wound up and stored in a cartridge.
Thereafter, the semiconductor element 20 and the like are fixed to the fixing pad 161 by being supplied frame by frame from the cartridge using the index hole 15, as shown in FIG. After that, the electrode lead 16
3 to conduct a functional test of the entire circuit including the semiconductor element 20 and other circuit elements, and perform functional trimming if necessary. If the specified circuit function cannot be obtained through this inspection, the semiconductor element 2
Either replace the 0 etc. and regenerate it, or mark it and stop the subsequent assembly process to improve the yield of the finished product. After this inspection, silicone resin is applied to the semiconductor element 20 and circuit elements requiring protection to protect the elements and bonding thin wires.
その後第７図に示す如く、フイルム状のままで
電極リード１６２の他端に外部端子２１を半田付
けした後外部端子２１を露出して樹脂２２で全体
をモールドし、然る後封止樹脂２２の端部でフイ
ルム基板１４を切断して個々の完成品に分離す
る。なお外部端子２１はフイルム基板１４の帯状
パターン１７で短絡しない様に折曲げ整形してお
く。 Thereafter, as shown in FIG. 7, the external terminal 21 is soldered to the other end of the electrode lead 162 while still in the film form, and then the external terminal 21 is exposed and the entire body is molded with resin 22. After that, the sealing resin 22 The film substrate 14 is cut at the end to separate it into individual finished products. Note that the external terminal 21 is bent and shaped so as not to be short-circuited by the strip pattern 17 of the film substrate 14.
更に本発明のフイルム基板は、接着剤１３が約
15〜30μと薄いために他方の銅箔１２を用いて容
易に多層化できる。即ち第８図に示す如く他方の
銅箔１２をエツチングするとき同時に裏面パター
ンと電気的に独立した裏面導電路２５を設け、こ
の導電路２５とリードパターン１６の重量部分を
裏面より約１mmの径の鋭い金属針でついて裏面導
電路２５から接着剤１３層を破りリードパターン
１６に達する貫通孔２６を形成した後に貫通孔２
６に半田２７を流し込んで裏面導電路２５とリー
ドパターン１６とを電気的に接続して多層化を実
現する。 Further, in the film substrate of the present invention, the adhesive 13 is about
Since it is as thin as 15 to 30μ, it can be easily multilayered using the other copper foil 12. That is, as shown in FIG. 8, when etching the other copper foil 12, a back conductive path 25 that is electrically independent from the back pattern is provided at the same time, and the weight portion of this conductive path 25 and lead pattern 16 is separated from the back surface by a diameter of about 1 mm. After breaking the 13 layers of adhesive from the back conductive path 25 with a sharp metal needle to form a through hole 26 that reaches the lead pattern 16, the through hole 2 is
Solder 27 is poured into 6 to electrically connect the back conductive path 25 and the lead pattern 16 to realize multilayering.
以上に詳述した如く本発明に依れば、二枚の銅
箔のみでフイルム基板構造を実現でき、一方の銅
箔で他方の銅箔で形成したリードパターンを支持
させることによりフイルムキヤリア方式に適用で
きる安価なフイルム基板構造を提供できる。しか
も導体である銅箔を支持手段として用いるので容
易に多層配線もできる。 As detailed above, according to the present invention, a film substrate structure can be realized using only two copper foils, and by supporting the lead pattern formed by one copper foil with the other copper foil, a film carrier method can be realized. An applicable and inexpensive film substrate structure can be provided. Furthermore, since copper foil, which is a conductor, is used as a supporting means, multilayer wiring can be easily achieved.
第１図は従来のポリイミド等の耐熱性プラスチ
ツク層を用いたフイルム基板構造を示す断面図、
第２図は本発明のフイルム基板構造を示す断面
図、第３図乃至第７図は本発明のフイルム基板を
用いた半導体装置の組立方法を説明する上面図、
第８図は本発明のフイルム基板を用いた多層構造
を説明する断面図である。
主な図番の説明、１１，１２は銅箔、１３は接
着剤、１４はフイルム基板、１５はインデツクス
孔、１６はリードパターンである。
Figure 1 is a cross-sectional view showing a conventional film substrate structure using a heat-resistant plastic layer such as polyimide.
FIG. 2 is a cross-sectional view showing the film substrate structure of the present invention, and FIGS. 3 to 7 are top views illustrating a method of assembling a semiconductor device using the film substrate of the present invention.
FIG. 8 is a sectional view illustrating a multilayer structure using the film substrate of the present invention. Explanation of the main figure numbers: 11 and 12 are copper foils, 13 is an adhesive, 14 is a film substrate, 15 is an index hole, and 16 is a lead pattern.
Claims (1)
硬化性樹脂で前記両銅箔を絶縁してフイルム状と
し、一方の銅箔をエツチングすることによつて、
半導体素子を載置する固着パツドと外部端子を固
着する電極から前記固着パツド近傍に残存された
電極リードから成るリードパターンが一定間隔で
形成され、且つ一方の銅箔の両端を残して帯状パ
ターンが設けられ、前記固着パツド及び外部端子
を固着する電極と少なくとも重畳する帯状の支持
体を前記他方の銅箔を残して形成することを特徴
とするフイルム基板構造。1. By bonding two copper foils with a thermosetting resin, insulating both copper foils with the thermosetting resin to form a film, and etching one of the copper foils,
A lead pattern consisting of a fixing pad for mounting a semiconductor element and an electrode for fixing an external terminal, remaining in the vicinity of the fixing pad, is formed at regular intervals, and a strip pattern is formed by leaving both ends of one copper foil. 1. A film substrate structure characterized in that a band-shaped support is formed, which overlaps at least the fixing pad and the electrode for fixing the external terminal, leaving the other copper foil.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP567281A JPS57120361A (en) | 1981-01-17 | 1981-01-17 | Structure of film substrate |
| KR1019810005282A KR850001541B1 (en) | 1981-01-17 | 1981-12-31 | Composite film |
| GB8200313A GB2093401B (en) | 1981-01-17 | 1982-01-06 | Composite film |
| DE3201133A DE3201133A1 (en) | 1981-01-17 | 1982-01-15 | COMPOSITE LAYER ARRANGEMENT, IN PARTICULAR FOR USE IN A SEMICONDUCTOR ARRANGEMENT, AND METHOD FOR THE PRODUCTION THEREOF |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP567281A JPS57120361A (en) | 1981-01-17 | 1981-01-17 | Structure of film substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57120361A JPS57120361A (en) | 1982-07-27 |
| JPS6256656B2 true JPS6256656B2 (en) | 1987-11-26 |
Family
ID=11617586
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP567281A Granted JPS57120361A (en) | 1981-01-17 | 1981-01-17 | Structure of film substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57120361A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05512Y2 (en) * | 1987-08-06 | 1993-01-08 |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2618883B2 (en) * | 1987-03-30 | 1997-06-11 | 株式会社東芝 | Semiconductor device |
| JPH0666362B2 (en) * | 1988-07-28 | 1994-08-24 | 日本電気株式会社 | Film carrier tape |
| SG184257A1 (en) * | 2010-03-30 | 2012-11-29 | Toray Industries | Metal support flexible board, metal support carrier tape for tape automated bonding using same, metal support flexible circuit board for mounting led, and copper foil-laminated metal support flexible circuit board for forming circuit |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49121968A (en) * | 1973-03-30 | 1974-11-21 |
-
1981
- 1981-01-17 JP JP567281A patent/JPS57120361A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49121968A (en) * | 1973-03-30 | 1974-11-21 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05512Y2 (en) * | 1987-08-06 | 1993-01-08 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57120361A (en) | 1982-07-27 |
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