JPS6356723B2 - - Google Patents
Info
- Publication number
- JPS6356723B2 JPS6356723B2 JP55086314A JP8631480A JPS6356723B2 JP S6356723 B2 JPS6356723 B2 JP S6356723B2 JP 55086314 A JP55086314 A JP 55086314A JP 8631480 A JP8631480 A JP 8631480A JP S6356723 B2 JPS6356723 B2 JP S6356723B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output
- current
- logic
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000000295 complement effect Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 9
- 230000002457 bidirectional effect Effects 0.000 description 8
- 238000000034 method Methods 0.000 description 7
- 230000001052 transient effect Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
- H03K3/0233—Bistable circuits
- H03K3/02337—Bistables with hysteresis, e.g. Schmitt trigger
Landscapes
- Logic Circuits (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8631480A JPS5711535A (en) | 1980-06-25 | 1980-06-25 | Integrated logical circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8631480A JPS5711535A (en) | 1980-06-25 | 1980-06-25 | Integrated logical circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5711535A JPS5711535A (en) | 1982-01-21 |
JPS6356723B2 true JPS6356723B2 (de) | 1988-11-09 |
Family
ID=13883366
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8631480A Granted JPS5711535A (en) | 1980-06-25 | 1980-06-25 | Integrated logical circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5711535A (de) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60100818A (ja) * | 1983-11-07 | 1985-06-04 | Sumitomo Electric Ind Ltd | ヒステリシス付きコンパレ−タ |
JPH0786909A (ja) * | 1993-06-30 | 1995-03-31 | Nec Corp | 半導体集積回路の出力回路 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54151360A (en) * | 1978-04-11 | 1979-11-28 | Mitsubishi Electric Corp | Schmitt trigger circuit |
-
1980
- 1980-06-25 JP JP8631480A patent/JPS5711535A/ja active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54151360A (en) * | 1978-04-11 | 1979-11-28 | Mitsubishi Electric Corp | Schmitt trigger circuit |
Also Published As
Publication number | Publication date |
---|---|
JPS5711535A (en) | 1982-01-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7595661B2 (en) | Low voltage differential signaling drivers including branches with series resistors | |
US7420387B2 (en) | Semiconductor device capable of controlling OCD and ODT circuits and control method used by the semiconductor device | |
US5519728A (en) | High-speed low-voltage differential swing transmission line transceiver | |
JP3788928B2 (ja) | 抵抗可変器 | |
JP5031258B2 (ja) | 半導体装置におけるインピーダンス制御回路及びインピーダンス制御方法 | |
US5939922A (en) | Input circuit device with low power consumption | |
JP2007505556A (ja) | レベル・シフター | |
US6285209B1 (en) | Interface circuit and input buffer integrated circuit including the same | |
JP4676646B2 (ja) | インピーダンス調整回路および半導体装置 | |
EP0762290B1 (de) | Eingangspufferschaltung | |
US6657460B2 (en) | Spatially filtered data bus drivers and receivers and method of operating same | |
JP4237402B2 (ja) | 対称送信ライン駆動用出力バッファ | |
US6300795B1 (en) | Multiple-bit, current mode data bus | |
US6504405B1 (en) | Differential amplifier with selectable hysteresis and buffered filter | |
KR100431568B1 (ko) | 고 저항 또는 고 커패시턴스 신호 라인용 저감 전압입력/저감 전압 출력 리피터 및 그 방법 | |
JPS6356723B2 (de) | ||
JPH0879047A (ja) | 半導体集積回路およびその製造方法 | |
JP3146829B2 (ja) | 半導体集積回路 | |
JPH0220171B2 (de) | ||
US6373276B1 (en) | CMOS small signal switchable impedence and voltage adjustable terminator with hysteresis receiver network | |
US7078935B2 (en) | Simultaneous bi-directional transceiver | |
KR20030022774A (ko) | 높은 저항 또는 높은 용량 신호 라인을 위한 혼합 스윙전압 리피터와 이를 위한 방법 | |
JP2000307413A (ja) | 電圧変換回路及び通信回路網 | |
US20020005747A1 (en) | Semiconductor device with signal transfer line | |
JP2000307410A (ja) | 集積回路 |