JPS6356723B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of constructing a current-switched integrated logic circuit.

In recent years, advances in integrated circuit technology have led to the realization of extremely high-speed and high-density integrated circuit elements, but the problem is that the increased speed and density of integrated circuits inevitably increases the power consumption per integrated circuit. It is full of. As is well known, the power consumption of integrated circuits is closely related to the power supply voltage and logic amplitude, and in recent years, large-scale integrated circuits have been designed with small power supply voltages and logic amplitudes in order to realize low-power devices. It is in. However, in such a design concept, the noise margin is often sacrificed, and a new problem arises in that the degree of freedom in computer system design, etc. is taken away.
Moreover, this trend is expected to further accelerate in the future, and effective measures to ensure noise margin have become one of the important issues required for integrated circuit technology.

An object of the present invention is to provide a new measure for improving the noise margin in a small amplitude current switching type logic circuit, which has not been possible with conventional circuit configurations.

In the logic circuit according to the present invention, one output of a first current switching type logic circuit having complementary outputs is inputted to second and third current switching type logic circuits having different circuit currents, and the first current switching type logic circuit has a complementary output. The other output of the switching circuit is supplied as a reference voltage to the second and third current switching logic circuits, and one output of the second current switching logic circuit and the output have different phases from each other. The output of the third current switching type logic circuit is
One end is connected to the other end of a resistive load circuit connected to a power supply, and the connection point is connected as a reference voltage of the first current switching type logic circuit, so that the first current switching type logic circuit is configured to have hysteresis in its input/output characteristics.

As mentioned above, the circuit of the present invention is configured so that the threshold value has two values for one logic operation, so by appropriately setting these two values, the noise margin can be increased for each logic level of the input signal. It is now possible to spread the signals equally, and extremely stable operation can be expected against variations in the amplitude and level of the input signal due to manufacturing variations and variations in external usage conditions.
Therefore, the present invention not only allows for the simple reception of logic signals, but also for simultaneous bidirectional drivers/receivers that can transmit and receive on a single signal line, for which it was difficult to secure sufficient noise margin with conventional methods. This can be realized by using this method. Furthermore, since the present invention can be configured by a simple combination of basic current switching type circuits, it also has the advantage that it can be easily realized using the master slice method.

The present invention will be described in detail below with reference to the drawings.

Current-switched logic circuits are generally shown in Figures 1 and 2.
It has a circuit configuration as shown in the figure. In FIG. 1, V _R indicates a reference voltage, which is normally set approximately at the center of the logic amplitude of the input V _IN . However, in the method shown in FIG. 1, the logic amplitude of the input signal becomes small due to manufacturing variations in integrated circuits, and when V _R becomes low due to manufacturing variations, external conditions, etc., the noise margin is significantly reduced. FIG. 2 shows a differential current switching circuit according to the conventional method, where V _IN1 and V _IN2 indicate differential inputs. Here, it is assumed that these two inputs have opposite phases. Assuming that noise can only be added to one of V _IN1 and V _IN2 at the same time, the noise margin will generally be greater than that of the circuit shown in FIG. 1. However, if anti-phase noise is added to V _IN1 and V _IN2 at the same time, the noise margin will be on the same level as the circuit in Figure 1, and if noise exceeding the threshold is added, the noise margin will be larger than in the circuit in Figure 1. Noise appears on the output. Furthermore, the circuit shown in FIG. 2 always requires two wires for input signals, and from an economic standpoint, it is not optimal to use it for connections between chips and signals between devices. The third circuit is the basic circuit of the present invention, which is constructed to compensate for the drawbacks of the circuits shown in FIGS. 1 and 2. A feature of the basic operation of this circuit is that the reference voltage V _RA1 of the logic gate G1 in the figure takes a binary value depending on the logic operation of the input signal. Connect outputs O1 and O2 of logic gate G1 (hereinafter all logic gates will be referred to as Gn in the figure) to G2 and G3 as shown in the figure, and
Among the outputs of 2 and G3, output lines I ₁ and I ₂ having mutually different phases are connected to point a. Also connected to point a is one end of a resistor whose other end is connected to a power source. Due to the switching operation of G1, either _I1 or _I2 is turned on, and the value of _VRA1 is determined. That is, when V _IN1 is at a low level, _I1 is turned on, and the potential at point a is determined by _RriI2 . Also, when V _IN1 is at a high level, I ₂ is turned on and the potential at point a is RriI ₃
It is determined by At this time, if I ₂ ≠ I ₃ , V _RA1 takes on two values depending on the level of V _IN1 , and the input/output characteristics of G1 have hysteresis. In the case of Figure 3,
If I ₂ <I ₃ , this hysteresis effect becomes effective in increasing the noise margin of each logic level of the input. It goes without saying that the width of the hysteresis and the two reference voltage levels can be freely set by appropriately selecting the value of Rri and the values of I ₂ and I ₃ here. Figure 4 shows the input/output characteristics of G1 in Figure 3. Since G2 and G3 differ from each other near the threshold, the input-to-output gain is extremely high, which is advantageous for expanding the noise margin. It can be seen that this is a characteristic.
Next, a description will be given using an application example of a simultaneous bidirectional driver/receiver circuit in which the circuit of the present invention is particularly effective. FIG. 5 shows the connection of a conventional bus circuit, and since the driver and receiver exist independently, two wires are always required for one driver/receiver set for transmitting and receiving signals. FIG. 6 shows a general block diagram and connection example of a simultaneous bidirectional driver/receiver circuit. According to this method, it is possible to send and receive signals with a single wire, and the number of wires is halved, so it is clearly advantageous in terms of economy. In Figure 7,
The basic circuit of FIG. 6 using a current switching type circuit is specifically shown. This circuit corresponds to block A or B in FIG. In FIG. 7, G4 indicates a gate for driver output, and G5 indicates a gate for switching the level of the reference voltage when the receiver circuit is on and off. When V _D1 is at a high level, I ₃ turns off the current, and the reference voltage V _RA2 of G5 becomes a fixed value of Rr ₂ · I _C. When V _D1 is at a low level, I ₄ turns on and G
The reference voltage V _RA2 of No. 5 has a value determined by Rr ₂ (I _C +I ₆ ). Although this basic operation enables simultaneous bidirectional transmission and reception, there are still some problems in use. In other words, in this method, the driver output and receiver input are directly connected internally (point c in Figure 7), and in actual use, they are also directly connected to the other driver output, which is a resistor output, by a bus line. The maximum and minimum possible combinations of resistance and amplitude variations must always be considered for each element. Therefore, the logic amplitude of the synthesized bus line becomes a value much larger than the variation within a single integrated circuit, and the noise margin is significantly reduced. FIG. 8 shows the transient characteristics of the circuit shown in FIG. 7 in the actual operating state (FIG. 6). In the area in this figure, V _D1 is at a high level.
This shows the operation when V _R1 is low level. The shaded area shows the level at point c when various variations are considered, such as the output resistance and amplitude of the other driver circuit, the output resistance and amplitude of the own driver circuit, and the GND deviation between both elements. It shows the range of variation. (The influence of transient reflected waves is ignored here.) If we pay attention to the operation (1) in Figure 8, the noise margin of each logic level with respect to the reference voltage (threshold) is extremely small, causing malfunctions. It can be seen that the risk of The circuit shown in Fig. 9 is a circuit in which the functions of the present invention are added to the circuit shown in Fig. 7.
It also has simultaneous bidirectional driver/receiver functionality. In Figure 9, G8, G10, G
11 constitutes the circuit function of the present invention. G7 is a driver gate, and G9 is a gate having a function of changing the threshold value of G8 depending on the level of V _D2 . When V _D2 is high level, transistor Q ₁ of G9
is turned off, and the potential at point d becomes the potential determined by I ₁₀ or I ₁₁ , which becomes the threshold of G8 for the bus signal. This is called the first level. On the other hand, when D _D2 is at a low level, the transistor Q ₁ of G3 is turned on, and the potential at point d drops from the threshold by Rr ₃ ·I ₉ , and this value becomes the threshold of G8 for the bus signal. This is called the second level. When operating at the 1st level, if the bus signal is high level, the G8 output e
is at a low level, the output f is at a high level, and the potential at point d is a value determined by Rr ₃ · I ₁₁ . Conversely, when the bus signal is at a low level, the outputs e and f are inverted, and the potential at point d takes a value determined by Rr ₃ ·I ₁₀ . Here, if I ₁₁ >I ₁₀ , the input/output characteristics of G8 have hysteresis. This operation is exactly the same as the operation shown in FIG. Next, when G8 operates at the second level, when the bus signal is high level, the output line _I6 of the driver is
Since _I7 is flowing, the high level of the bus is DC-wise
The value is determined by I ₇・R _B. At this time, the potential at point d is
Rr ₃・(I ₉ + I ₁₁ ). Conversely, when the bus signal is at a low level, the bus level is determined by the on-current and output resistance of the other driver circuit, as well as R _B and I ₇ , and the potential at point d is R ₂ (I ₉ + I ₁₀ ) is the value determined by Similarly, if I ₁₁ >I ₁₀ , the input/output characteristics of G8 have hysteresis.

The circuit constants that determine the potential at point d, such as I ₉ , I ₁₀ , I ₁₁ , and Rr ₃ above, vary depending on various conditions such as the amplitude of the output of the other driver, the resistance, and the GND deviation between the other elements. Needless to say, it must be set in consideration of the variations in its own characteristics.

FIG. 10 shows the transient operation of V _D2 , V _B2 , V _OUTR , and V _RA3 . In the figure, the regions , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , _{, ,} , , , , and 8 and 1 and 7 and _{1 and 1 and 1 and 1 and 1} , , , , , , , , , , , , , , , , , , , , , , , , , ), , , , ,, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,, , , , , , , ,                  . If you pay attention to the operation in (1), you will understand that due to the hysteresis effect, a much larger noise margin can be secured than the operation shown in Figure 8 even under the worst case of bus level variation shown in the shaded area. I can do it. FIG. 11 shows the input/output characteristics of G1 in FIG. The arrow indicates the direction of operation, and the shaded area indicates the width of the hysteresis.

As explained above, the circuit of the present invention can easily maintain the necessary noise margin even with variations in external conditions by providing hysteresis to the input/output characteristics of the gate depending on the conditions. In addition to improving the degree of freedom in device design by enabling circuit configurations that can be configured to It has various advantages such as making it easier to use.

[Brief explanation of the drawing]

Figure 1 is a diagram showing a basic current switching type circuit, Figure 2 is a diagram showing a current switching type circuit using a differential method,
FIG. 3 is a diagram showing the basic configuration of the circuit of the present invention,
Fig. 4 shows the input/output characteristics of the circuit shown in Fig. 3, Fig. 5 shows an example of connection of a conventional bus circuit, and Fig. 6 shows an example of connection of a simultaneous bidirectional driver/receiver circuit. 7 is a diagram showing the basic configuration of a simultaneous bidirectional driver/receiver circuit, FIG. 8 is a diagram showing the transient characteristics of FIG. 7, and FIG.
The figure shows a simultaneous bidirectional driver/
A diagram showing a specific example of the receiver circuit, FIG. 10 is a diagram showing the transient characteristics of the circuit in FIG. 9, and FIG.
FIG. 3 is a diagram showing input/output characteristics of the circuit shown in the figure. V _IN1 , V _IN2 ...Differential input, _G1 , _G2 , _G3 ...Gate, _I1 to _I3 ...Current source.

Claims (1)

[Claims] 1. One output of the first current-switching logic circuit having complementary outputs is input to second and third current-switching logic circuits having different circuit currents, and the other output of the first current-switching logic circuit The output of is supplied as a reference voltage to the second and third current switching type logic circuits, and one output of the second current switching type logic circuit and the third current switching type having a phase different from the one output. The output of the first current-switching logic circuit is connected to the other end of a resistive load circuit whose one end is connected to a power source, and the connection point is connected as a reference voltage of the first current-switching logic circuit. An integrated logic circuit characterized by having hysteresis in the input/output characteristics of the current switching type logic circuit.