JPS6340508B2 - - Google Patents

Info

Publication number
JPS6340508B2
JPS6340508B2 JP55149303A JP14930380A JPS6340508B2 JP S6340508 B2 JPS6340508 B2 JP S6340508B2 JP 55149303 A JP55149303 A JP 55149303A JP 14930380 A JP14930380 A JP 14930380A JP S6340508 B2 JPS6340508 B2 JP S6340508B2
Authority
JP
Japan
Prior art keywords
frame synchronization
bits
circuit
synchronization signal
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55149303A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5773542A (en
Inventor
Kazunori Chiba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP55149303A priority Critical patent/JPS5773542A/ja
Publication of JPS5773542A publication Critical patent/JPS5773542A/ja
Publication of JPS6340508B2 publication Critical patent/JPS6340508B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0626—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP55149303A 1980-10-27 1980-10-27 Frame synchronizing system in cyclic transmission Granted JPS5773542A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55149303A JPS5773542A (en) 1980-10-27 1980-10-27 Frame synchronizing system in cyclic transmission

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55149303A JPS5773542A (en) 1980-10-27 1980-10-27 Frame synchronizing system in cyclic transmission

Publications (2)

Publication Number Publication Date
JPS5773542A JPS5773542A (en) 1982-05-08
JPS6340508B2 true JPS6340508B2 (enrdf_load_stackoverflow) 1988-08-11

Family

ID=15472194

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55149303A Granted JPS5773542A (en) 1980-10-27 1980-10-27 Frame synchronizing system in cyclic transmission

Country Status (1)

Country Link
JP (1) JPS5773542A (enrdf_load_stackoverflow)

Also Published As

Publication number Publication date
JPS5773542A (en) 1982-05-08

Similar Documents

Publication Publication Date Title
EP0216456B1 (en) Multiplex structure
US4107469A (en) Multiplex/demultiplex apparatus
US4694472A (en) Clock adjustment method and apparatus for synchronous data communications
CA1313573C (en) Complex multiplexer/demultiplexer apparatus
JPH0828691B2 (ja) フレーム同期方式
JPH04211534A (ja) データ伝送方法
GB1581521A (en) Tdma multiplexer-demultiplexer with multiple ports
US5442636A (en) Circuit and method for alignment of digital information packets
JPS639694B2 (enrdf_load_stackoverflow)
GB1047639A (en) Improvements in or relating to time division transmission systems
EP0302112B1 (en) Multiplex dividing apparatus in a synchronous multiplexing system
JPH05199199A (ja) スタッフ同期制御方式
US4736372A (en) Method and apparatus of transmission for a digital signal
JPH04211535A (ja) 特定フレーム構造体への情報ビットの挿入装置
JPS6340508B2 (enrdf_load_stackoverflow)
JPS6125340A (ja) 速度変換回路
KR940010201B1 (ko) 전송장치의 병렬처리 방식에 의한 ds3/ds4 신호의 다중화 회로
JPH0530068A (ja) 調歩式データ多重化方式
JP2952935B2 (ja) 非同期データ伝送システム
JP2583358B2 (ja) Ｐｃｍ信号伝送回路
SU936461A1 (ru) Способ передачи и приема асинхронных цифровых сигналов
JPH0756962B2 (ja) データ通信システム
JPH0583224A (ja) スタツフ多重化装置
JPH0712163B2 (ja) 多重化マルチフレ−ム同期回路
JPH02164147A (ja) 副信号発生方式