JPS5773542A - Frame synchronizing system in cyclic transmission - Google Patents

Frame synchronizing system in cyclic transmission

Info

Publication number
JPS5773542A
JPS5773542A JP55149303A JP14930380A JPS5773542A JP S5773542 A JPS5773542 A JP S5773542A JP 55149303 A JP55149303 A JP 55149303A JP 14930380 A JP14930380 A JP 14930380A JP S5773542 A JPS5773542 A JP S5773542A
Authority
JP
Japan
Prior art keywords
circuit
clock
frequency
synchronizing
multiplex
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55149303A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6340508B2 (enrdf_load_stackoverflow
Inventor
Kazunori Chiba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55149303A priority Critical patent/JPS5773542A/ja
Publication of JPS5773542A publication Critical patent/JPS5773542A/ja
Publication of JPS6340508B2 publication Critical patent/JPS6340508B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0626—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP55149303A 1980-10-27 1980-10-27 Frame synchronizing system in cyclic transmission Granted JPS5773542A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55149303A JPS5773542A (en) 1980-10-27 1980-10-27 Frame synchronizing system in cyclic transmission

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55149303A JPS5773542A (en) 1980-10-27 1980-10-27 Frame synchronizing system in cyclic transmission

Publications (2)

Publication Number Publication Date
JPS5773542A true JPS5773542A (en) 1982-05-08
JPS6340508B2 JPS6340508B2 (enrdf_load_stackoverflow) 1988-08-11

Family

ID=15472194

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55149303A Granted JPS5773542A (en) 1980-10-27 1980-10-27 Frame synchronizing system in cyclic transmission

Country Status (1)

Country Link
JP (1) JPS5773542A (enrdf_load_stackoverflow)

Also Published As

Publication number Publication date
JPS6340508B2 (enrdf_load_stackoverflow) 1988-08-11

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