JPS5773542A - Frame synchronizing system in cyclic transmission - Google Patents

Abstract

PURPOSE:To increase the multiplexity and to reduce the synchronism drawing-in time of low-level group data, by simplifying the hardware of a multiplex conversion device through the operation of a frame synchronizing signal of the low-level group data and making unnecessary the staff designation pulse. CONSTITUTION:An input pulse train in nominal clock frequency f1 taking the frame synchronism signal bit number as (minimum bit number being unique pattern + 1-bit) enters an input conversion circuit 21. The frequency f1 is picked up at a timing pickup circuit 22 and the input pulse train is sequentially stored by several bits to a memory circuit 23 with the pulse of this frequency f1. The stored input pulse train is read out with a clock obtained from the clock of a synchronizing multiplex circuit 27 through frequency-division at a control circuit 26 and transferred and multiplexed to the synchronizing multiplex circuit 27. The phase difference between a write-in clock and readout clock at a phase comparison circuit 25 is monitored to control the control circuit 26. The signals are separated to each channel at a synchronizing multiplex separation circuit 28 at the reception side.