JPS5773542A - Frame synchronizing system in cyclic transmission - Google Patents
Frame synchronizing system in cyclic transmissionInfo
- Publication number
- JPS5773542A JPS5773542A JP55149303A JP14930380A JPS5773542A JP S5773542 A JPS5773542 A JP S5773542A JP 55149303 A JP55149303 A JP 55149303A JP 14930380 A JP14930380 A JP 14930380A JP S5773542 A JPS5773542 A JP S5773542A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- clock
- frequency
- synchronizing
- multiplex
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
- H04J3/0626—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Time-Division Multiplex Systems (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
PURPOSE:To increase the multiplexity and to reduce the synchronism drawing-in time of low-level group data, by simplifying the hardware of a multiplex conversion device through the operation of a frame synchronizing signal of the low-level group data and making unnecessary the staff designation pulse. CONSTITUTION:An input pulse train in nominal clock frequency f1 taking the frame synchronism signal bit number as (minimum bit number being unique pattern + 1-bit) enters an input conversion circuit 21. The frequency f1 is picked up at a timing pickup circuit 22 and the input pulse train is sequentially stored by several bits to a memory circuit 23 with the pulse of this frequency f1. The stored input pulse train is read out with a clock obtained from the clock of a synchronizing multiplex circuit 27 through frequency-division at a control circuit 26 and transferred and multiplexed to the synchronizing multiplex circuit 27. The phase difference between a write-in clock and readout clock at a phase comparison circuit 25 is monitored to control the control circuit 26. The signals are separated to each channel at a synchronizing multiplex separation circuit 28 at the reception side.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55149303A JPS5773542A (en) | 1980-10-27 | 1980-10-27 | Frame synchronizing system in cyclic transmission |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55149303A JPS5773542A (en) | 1980-10-27 | 1980-10-27 | Frame synchronizing system in cyclic transmission |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5773542A true JPS5773542A (en) | 1982-05-08 |
JPS6340508B2 JPS6340508B2 (en) | 1988-08-11 |
Family
ID=15472194
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55149303A Granted JPS5773542A (en) | 1980-10-27 | 1980-10-27 | Frame synchronizing system in cyclic transmission |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5773542A (en) |
-
1980
- 1980-10-27 JP JP55149303A patent/JPS5773542A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6340508B2 (en) | 1988-08-11 |
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