JPS6338394U - - Google Patents
Info
- Publication number
- JPS6338394U JPS6338394U JP13115586U JP13115586U JPS6338394U JP S6338394 U JPS6338394 U JP S6338394U JP 13115586 U JP13115586 U JP 13115586U JP 13115586 U JP13115586 U JP 13115586U JP S6338394 U JPS6338394 U JP S6338394U
- Authority
- JP
- Japan
- Prior art keywords
- protrusion
- projection
- package structure
- wire
- fixed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 2
- 239000002184 metal Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32153—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
- H01L2224/32175—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
- H01L2224/32188—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic the layer connector connecting to a bonding area protruding from the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Wire Bonding (AREA)
- Mounting Of Printed Circuit Boards And The Like (AREA)
Description
第１図は本考案の一実施例の要部断面図、第２
図は従来の一部断面図である。
１，１１……ベース、２，１２……突起、２ａ
，１２ａ……曲面部、３，１３……素子チツプ、
４，１４……回路基板、５，１５……単板コンデ
ンサ、６，１６……金属ワイヤ。
Figure 1 is a sectional view of the main parts of an embodiment of the present invention, Figure 2
The figure is a partial sectional view of a conventional device. 1, 11... Base, 2, 12... Protrusion, 2a
, 12a... curved surface portion, 3, 13... element chip,
4, 14... Circuit board, 5, 15... Single plate capacitor, 6, 16... Metal wire.
Claims (1)
の突起上に搭載した電子部品を、この突起に隣接
する位置のベース上に固定した回路基板や単板コ
ンデンサ等の他部品とワイヤ接続するパツケージ
構造において、前記突起を逆テーパ状に形成する
とともに、前記他部品を側面からこの突起に突き
当てた状態で固定して前記電子部品との間をワイ
ヤ接続したことを特徴とするパツケージ構造。 (2) 突起の上部幅寸法が、突起下部に生じる曲
面部を含む幅寸法となるようなテーパ角度に形成
してなる実用新案登録請求の範囲第１項記載のパ
ツケージ構造。[Claims for Utility Model Registration] (1) A protrusion is formed on the base of the package, and an electronic component mounted on the protrusion is fixed to the base adjacent to the protrusion, such as a circuit board or a single-plate capacitor. In a package structure that is connected to other parts by wire, the protrusion is formed in a reverse tapered shape, and the other part is fixed in a state in which it abuts against the protrusion from the side, and the electronic part is connected to the electronic part by wire. A package structure featuring: (2) The package structure according to claim 1, wherein the projection is formed at a tapered angle such that the width of the upper part of the projection includes the curved surface formed at the lower part of the projection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13115586U JPS6338394U (en) | 1986-08-29 | 1986-08-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13115586U JPS6338394U (en) | 1986-08-29 | 1986-08-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6338394U true JPS6338394U (en) | 1988-03-11 |
Family
ID=31029333
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13115586U Pending JPS6338394U (en) | 1986-08-29 | 1986-08-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6338394U (en) |
-
1986
- 1986-08-29 JP JP13115586U patent/JPS6338394U/ja active Pending