JPS62174346U - - Google Patents
Info
- Publication number
- JPS62174346U JPS62174346U JP1986062371U JP6237186U JPS62174346U JP S62174346 U JPS62174346 U JP S62174346U JP 1986062371 U JP1986062371 U JP 1986062371U JP 6237186 U JP6237186 U JP 6237186U JP S62174346 U JPS62174346 U JP S62174346U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- electrode
- heat sink
- circuit board
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims description 9
- 230000002093 peripheral effect Effects 0.000 claims 1
- 238000005219 brazing Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000000945 filler Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
Description
第１図は本考案の半導体装置の正面図、第２図
ないし第５図は従来の半導体装置の一例を示し、
第２図は全体斜視図、第３図は正面図、第４図は
半導体素子とヒートシンクとの間に介装されたろ
う材がはみ出した状態を示す図、第５図はワイヤ
の接続状態の他の例を示す正面図である。
１……回路基板、２……表面電極、３，１０…
…ろう材、４……ヒートシンク、５……上面、６
……上端面、７……傾斜面、８……面取り、９…
…素子搭載部、１１……半導体素子、１２……電
極、１３……ワイヤ。
FIG. 1 is a front view of the semiconductor device of the present invention, and FIGS. 2 to 5 show examples of conventional semiconductor devices.
Fig. 2 is an overall perspective view, Fig. 3 is a front view, Fig. 4 is a view showing a state in which the brazing filler metal interposed between the semiconductor element and the heat sink is protruding, and Fig. 5 shows the state of the wire connection and other details. It is a front view showing an example. 1... Circuit board, 2... Surface electrode, 3, 10...
...Brazing metal, 4...Heat sink, 5...Top surface, 6
... Upper end surface, 7 ... Inclined surface, 8 ... Chamfer, 9 ...
...Element mounting portion, 11...Semiconductor element, 12...Electrode, 13...Wire.
Claims (1)
ヒートシンク上に半導体素子が搭載されるととも
に、該半導体素子の上面の電極と前記回路基板の
上面の電極とがワイヤによつて接続された構造の
半導体装置において、 前記ヒートシンクの最上部に設けられた素子搭
載領域の形状が前記半導体素子の下面形状と略同
一に形成されるとともに、ヒートシンクの上部周
縁に面取りが施されたことを特徴とする半導体装
置。 (2) 素子搭載領域の周壁が下方に行くに従い外
方に広がる傾斜面に形成されてなる実用新案登録
請求の範囲第１項記載の半導体装置。[Claims for Utility Model Registration] (1) A heat sink is mounted on a circuit board, a semiconductor element is mounted on the heat sink, and an electrode on the upper surface of the semiconductor element and an electrode on the upper surface of the circuit board are connected by wires. In the semiconductor device having a structure connected by A semiconductor device characterized by: (2) The semiconductor device according to claim 1, wherein the peripheral wall of the element mounting area is formed into an inclined surface that widens outward as it goes downward.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986062371U JPH0442927Y2 (en) | 1986-04-24 | 1986-04-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986062371U JPH0442927Y2 (en) | 1986-04-24 | 1986-04-24 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62174346U true JPS62174346U (en) | 1987-11-05 |
| JPH0442927Y2 JPH0442927Y2 (en) | 1992-10-12 |
Family
ID=30896581
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986062371U Expired JPH0442927Y2 (en) | 1986-04-24 | 1986-04-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0442927Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005116875A (en) * | 2003-10-09 | 2005-04-28 | Denso Corp | Semiconductor device |
-
1986
- 1986-04-24 JP JP1986062371U patent/JPH0442927Y2/ja not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005116875A (en) * | 2003-10-09 | 2005-04-28 | Denso Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0442927Y2 (en) | 1992-10-12 |