JPH0442927Y2 - - Google Patents
Info
- Publication number
- JPH0442927Y2 JPH0442927Y2 JP1986062371U JP6237186U JPH0442927Y2 JP H0442927 Y2 JPH0442927 Y2 JP H0442927Y2 JP 1986062371 U JP1986062371 U JP 1986062371U JP 6237186 U JP6237186 U JP 6237186U JP H0442927 Y2 JPH0442927 Y2 JP H0442927Y2
- Authority
- JP
- Japan
- Prior art keywords
- heat sink
- semiconductor element
- shape
- electrode
- wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 43
- 230000002093 peripheral effect Effects 0.000 claims description 3
- 238000005219 brazing Methods 0.000 description 10
- 239000000463 material Substances 0.000 description 7
- 239000002184 metal Substances 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 230000008961 swelling Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
Description
【考案の詳細な説明】
（産業上の利用分野）
本考案は半導体装置に関し、特に電力半導体装
置の放熱用として用いられるヒートシンクの構造
に係る。[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a semiconductor device, and particularly to the structure of a heat sink used for heat dissipation in a power semiconductor device.
（従来の技術）
従来の電力半導体装置の構造を第２図ないし第
５図に示す。(Prior Art) The structure of a conventional power semiconductor device is shown in FIGS. 2 to 5.
第２図および第３図において、ａは回路基板、
ｂは放熱用のヒートシンク、ｃは半導体素子、ｄ
は半導体素子ｃの上面の電極（図示省略）と回路
基板ａの上面の電極ｆとを電気的に接続するワイ
ヤである。 In FIGS. 2 and 3, a is a circuit board;
b is a heat sink for heat dissipation, c is a semiconductor element, d
is a wire that electrically connects an electrode (not shown) on the top surface of the semiconductor element c and an electrode f on the top surface of the circuit board a.
ヒートシンクｂは、その機能を十分に果たし得
る形状にする必要があり、その上面は半導体素子
ｃの下面より大きな面積になされ、かつ十分な厚
みを有する直方体形状に形成されいてる。このヒ
ートシンクｂの上面にろう材ｅ（第４図参照）を
介して半導体素子ｃが接合されている。 The heat sink b needs to have a shape that can sufficiently fulfill its function, and is formed into a rectangular parallelepiped shape with an upper surface having a larger area than the lower surface of the semiconductor element c and a sufficient thickness. A semiconductor element c is bonded to the upper surface of the heat sink b via a brazing material e (see FIG. 4).
（考案が解決しようとする問題点）
ところが、上記した構造の半導体装置では、半
導体素子ｃを接合しているろう材ｅが、第４図に
示すように、該半導体素子ｃの周辺に盛り上が
り、このため、半導体素子ｃの周辺の絶縁距離が
短くなつて耐圧不足等の特性劣化を生じるという
問題があつた。また、半導体素子ｃの上面の電極
と回路基板ａの上面の電極ｆとを一般的なワイヤ
ボンデイング装置で接続した場合、ワイヤｄの配
線形状は第３図に示すアーチ形状となり、ヒート
シンクｂの周縁部に接触する心配があつた。これ
を避けるためには、ワイヤｄをもつと高く長いア
ーチ形状にするか、もしくは第５図に示すような
鉤形状にする必要があるが、鉤形状にするために
は、ループ機能付の特殊なボンデイング装置を必
要とするという問題があつた。(Problems to be Solved by the Invention) However, in the semiconductor device having the above structure, the brazing material e joining the semiconductor element c swells around the semiconductor element c, as shown in FIG. For this reason, there was a problem in that the insulation distance around the semiconductor element c became short, resulting in deterioration of characteristics such as insufficient withstand voltage. Furthermore, when the electrode on the top surface of the semiconductor element c and the electrode f on the top surface of the circuit board a are connected using a general wire bonding device, the wiring shape of the wire d becomes an arch shape as shown in FIG. 3, and the periphery of the heat sink b I was worried about coming into contact with the department. In order to avoid this, it is necessary to make the wire d into a high and long arch shape, or to make it into a hook shape as shown in Figure 5, but in order to make it into a hook shape, a special There was a problem that a special bonding device was required.
（問題点を解決するための手段）
本考案の半導体装置は、回路基板上にヒートシ
ンクが搭載され、該ヒートシンク上に半導体素子
が搭載されるとともに、該半導体素子の上面の電
極と前記回路基板の上面の電極とがワイヤによつ
て接続された構造の半導体装置において、前記ヒ
ートシンクの最上部に設けられた素子搭載領域の
形状が前記半導体素子の下面形状と略同一に形成
されるとともに、ヒートシンクの上部周縁に面取
りが施されたものである。(Means for Solving the Problems) In the semiconductor device of the present invention, a heat sink is mounted on a circuit board, a semiconductor element is mounted on the heat sink, and an electrode on the upper surface of the semiconductor element and an electrode on the upper surface of the circuit board are mounted on the heat sink. In a semiconductor device having a structure in which an electrode on the top surface is connected by a wire, the shape of the element mounting area provided at the top of the heat sink is formed to be approximately the same as the shape of the bottom surface of the semiconductor element, and The upper periphery is chamfered.
（作用）
ヒートシンクの最上部に設けられた素子搭載領
域の形状が半導体素子の下面形状と略同一に形成
され、その周壁が傾斜面に形成されているので、
ろう材は傾斜面に沿つて流下し、半導体素子の周
辺に盛り上がることがない。また、ヒートシンク
の上部周縁に面取りが施されているので、ヒート
シンクとワイヤとの間に十分な間隔をとることが
できる。(Function) Since the shape of the element mounting area provided at the top of the heat sink is formed to be approximately the same as the shape of the lower surface of the semiconductor element, and the peripheral wall thereof is formed as an inclined surface,
The brazing material flows down along the slope and does not bulge around the semiconductor element. Furthermore, since the upper periphery of the heat sink is chamfered, a sufficient distance can be maintained between the heat sink and the wire.
（実施例）
以下、本考案の一実施例を図面を参照して説明
する。(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.
第１図は本考案の半導体装置を示している。 FIG. 1 shows a semiconductor device of the present invention.
同図において、１は回路基板で、この回路基板
１の上面に配線された表面電極２の上にろう材３
を介してヒートシンク４が搭載（接合）されてい
る。 In the figure, 1 is a circuit board, and a brazing material 3 is placed on a surface electrode 2 wired on the top surface of the circuit board 1.
A heat sink 4 is mounted (bonded) via the heat sink 4.
ヒートシング４はその上面５の周縁を全周に亘
つて面取り８された略直方体形状に形成されると
ともに、その上面５の中央部に上方に突出した素
子搭載部９が形成されたものである。素子搭載部
９の上端面（素子搭載領域）６の形状は、後述す
る半導体素子１１の下面形状と略同一に形成さ
れ、その周壁は下方に行くに従い外方に広がつた
傾斜面７になされている。 The heat sink 4 is formed into a substantially rectangular parallelepiped shape with a chamfered edge 8 along the entire circumference of the upper surface 5, and an element mounting portion 9 that protrudes upward is formed in the center of the upper surface 5. . The shape of the upper end face (element mounting area) 6 of the element mounting portion 9 is formed to be approximately the same as the shape of the lower face of the semiconductor element 11, which will be described later, and its peripheral wall is formed into an inclined surface 7 that widens outward as it goes downward. ing.
このヒートシンク４の前記上端面６にろう材１
０を介して半導体素子１１が搭載（接合）され、
この半導体素子１１の上面の電極（図示省略）と
回路基板１の上面の電極１２とがワイヤ１３によ
つて接続されて、電力半導体装置を構成してい
る。 A brazing material 1 is attached to the upper end surface 6 of this heat sink 4.
A semiconductor element 11 is mounted (bonded) through 0,
An electrode (not shown) on the top surface of this semiconductor element 11 and an electrode 12 on the top surface of the circuit board 1 are connected by a wire 13 to constitute a power semiconductor device.
なお、前記ヒートシンク４の上端面６には、該
ヒートシンク４の材質により、ぬれ性すなわちろ
う付け性の良い表面処理を施してもよい。 Note that the upper end surface 6 of the heat sink 4 may be subjected to a surface treatment with good wettability, that is, brazing property, depending on the material of the heat sink 4.
上記した構成の半導体装置によれば、ヒートシ
ンク４の上端面６が半導体素子１１の下面と略同
一形状に形成されているので、半導体素子１１の
接合時の位置決めが容易になる。また、上端面６
の周縁が傾斜面７になされているので、半導体素
子１１を接合時、上端面６の周縁からはみ出した
ろう材１０は傾斜面７に沿つて下方に流れること
になり、半導体素子１１の周辺に盛り上がらな
い。さらに、シートシンク４の上面５の周縁に面
取り８を施しているので、一般的なボンデイング
装置を使用してワイヤ１３の接続を行つても、ワ
イヤ１３がヒートシンク４に接触する心配がな
い。これらにより、半導体装置の特性の向上、小
型化、および組立装置の合理化が可能となる。 According to the semiconductor device having the above configuration, the upper end surface 6 of the heat sink 4 is formed in substantially the same shape as the lower surface of the semiconductor element 11, so that positioning of the semiconductor element 11 during bonding becomes easy. In addition, the upper end surface 6
Since the periphery of the semiconductor element 11 is formed on the inclined surface 7, the brazing material 10 protruding from the periphery of the upper end surface 6 flows downward along the inclined surface 7 when the semiconductor element 11 is bonded, and is not raised around the semiconductor element 11. do not have. Furthermore, since the periphery of the upper surface 5 of the sheet sink 4 is chamfered 8, there is no fear that the wire 13 will come into contact with the heat sink 4 even if the wire 13 is connected using a general bonding device. These enable improvements in the characteristics of semiconductor devices, miniaturization, and rationalization of assembly equipment.
（考案の効果）
以上説明したように、本考案の半導体装置によ
れば、半導体素子とヒートシンクの上端面とに介
装されたろう材のはみ出し部分の盛り上がりがな
くなり、耐圧不足等の特性劣化を防止することが
できる。また、ヒートシンクの上部の周縁に面取
りを施しているので、ワイヤを長くしなくても、
該ワイヤとヒートシンクとの距離を保ち、接触を
防止することができる。(Effects of the invention) As explained above, according to the semiconductor device of the invention, there is no swelling of the protruding portion of the brazing filler metal interposed between the semiconductor element and the upper end surface of the heat sink, thereby preventing characteristic deterioration such as insufficient withstand voltage. can do. In addition, the upper periphery of the heat sink is chamfered, so you can use it without making the wires longer.
It is possible to maintain a distance between the wire and the heat sink to prevent contact.
第１図は本考案の半導体装置の正面図、第２図
ないし第５図は従来の半導体装置の一例を示し、
第２図は全体斜視図、第３図は正面図、第４図は
半導体素子とヒートシンクとの間に介装されたろ
う材がはみ出した状態を示す図、第５図はワイヤ
の接続状態の他の例を示す正面図である。
１……回路基板、２……表面電極、３，１０…
…ろう材、４……ヒートシンク、５……上面、６
……上端面、７……傾斜面、８……面取り、９…
…素子搭載部、１１……半導体素子、１２……電
極、１３……ワイヤ。
FIG. 1 is a front view of the semiconductor device of the present invention, and FIGS. 2 to 5 show examples of conventional semiconductor devices.
Fig. 2 is an overall perspective view, Fig. 3 is a front view, Fig. 4 is a view showing a state in which the brazing filler metal interposed between the semiconductor element and the heat sink is protruding, and Fig. 5 shows the state of the wire connection and other details. It is a front view showing an example. 1... Circuit board, 2... Surface electrode, 3, 10...
...Brazing metal, 4...Heat sink, 5...Top surface, 6
... Upper end surface, 7 ... Inclined surface, 8 ... Chamfer, 9 ...
...Element mounting portion, 11...Semiconductor element, 12...Electrode, 13...Wire.
Claims (1)
ートシンク上に半導体素子が搭載されるととも
に、該半導体素子の上面の電極と前記回路基板
の上面の電極とがワイヤによつて接続された構
造の半導体装置において、 前記ヒートシンクの最上部に設けられた素子
搭載領域の形状が前記半導体素子の下面形状と
略同一に形成されるとともに、ヒートシンクの
上部周縁に面取りが施されたことを特徴とする
半導体装置。 ２ 素子搭載領域の周壁が下方に行くに従い外方
に広がる傾斜面に形成されてなる実用新案登録
請求の範囲第１項記載の半導体装置。[Claims for Utility Model Registration] 1. A heat sink is mounted on a circuit board, a semiconductor element is mounted on the heat sink, and an electrode on the upper surface of the semiconductor element and an electrode on the upper surface of the circuit board are connected by a wire. In the semiconductor device having a structure in which the heat sink is connected by a wire, the shape of the element mounting area provided at the top of the heat sink is formed to be approximately the same as the shape of the bottom surface of the semiconductor element, and the upper periphery of the heat sink is chamfered. A semiconductor device characterized by: 2. The semiconductor device according to claim 1, wherein the peripheral wall of the element mounting area is formed into an inclined surface that widens outward as it goes downward.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986062371U JPH0442927Y2 (en) | 1986-04-24 | 1986-04-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986062371U JPH0442927Y2 (en) | 1986-04-24 | 1986-04-24 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62174346U JPS62174346U (en) | 1987-11-05 |
| JPH0442927Y2 true JPH0442927Y2 (en) | 1992-10-12 |
Family
ID=30896581
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986062371U Expired JPH0442927Y2 (en) | 1986-04-24 | 1986-04-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0442927Y2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4339660B2 (en) * | 2003-10-09 | 2009-10-07 | 株式会社デンソー | Semiconductor device |
-
1986
- 1986-04-24 JP JP1986062371U patent/JPH0442927Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62174346U (en) | 1987-11-05 |
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