JP4330293B2 - Power semiconductor device - Google Patents

Power semiconductor device Download PDF

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JP4330293B2
JP4330293B2 JP2001241952A JP2001241952A JP4330293B2 JP 4330293 B2 JP4330293 B2 JP 4330293B2 JP 2001241952 A JP2001241952 A JP 2001241952A JP 2001241952 A JP2001241952 A JP 2001241952A JP 4330293 B2 JP4330293 B2 JP 4330293B2
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power semiconductor
insulating substrate
semiconductor element
semiconductor device
pattern
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JP2003060158A (en
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慶久 小栗
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、インバータ等の電力用半導体装置に関し、より詳しくは、その装置内での電力用半導体素子を搭載した絶縁基板のベース板に対する固定構造に関する。
【０００２】
【従来の技術】
従来、電力用半導体装置において、電力用半導体素子を搭載した絶縁基板は、放熱及び位置固定の必要性からベース板に対してハンダ接合されることが一般的である。図４に、従来知られる電力用半導体装置の内部構造の一例を示す。この電力半導体装置５０において、電力用半導体素子５１が搭載される絶縁基板５２の表面側には、半導体素子搭載用の回路パターン５３（以下、表面パターンと称す）が形成され、他方、絶縁基板５２の裏面側には、ほぼ全面に広がる金属パターン５４（以下、裏面パターンと称す）が形成される。
表面パターン５３上には、電力用半導体素子５１がハンダ５５を用いて接合される。そして、絶縁基板５２は、その裏面側で、裏面パターン５４の全面に広がるハンダ層５６を介し、金属製のベース板５９に接合される。
【０００３】
【発明が解決しようとする課題】
しかしながら、かかる電力用半導体装置５０においては、電力用半導体素子５１のスイッチング動作時に発生する熱により絶縁基板５２やベース板５９が熱膨張することによって、両者を接合しているハンダ層５６にクラックが生じる惧れがある。このクラックは、放熱性の低下による各素子の破壊や絶縁不良をもたらす要因となる。
【０００４】
本発明は、上記技術的課題に鑑みてなされたもので、電力用半導体素子を搭載した絶縁基板とベース板とを接合するハンダ層内でのクラック発生を確実に防止し得る電力用半導体装置を提供することを目的とする。
【０００５】
【課題を解決するための手段】
本願の第１の発明は、その表面側で回路パターンが形成された上で電力用半導体素子が搭載される一方、その裏面側では金属パターンが形成された上でハンダ層を介して放熱および位置固定用のベース板に接合される絶縁基板を備えた電力用半導体装置において、金属パターンが矩形状であり、金属パターンのコーナ部に切欠き部が設けられていることを特徴とするものである。
【０００６】
また、本願の第２の発明は、更に、切欠き部が、金属パターンにおける、絶縁基板の表面側で電力用半導体素子が搭載される領域に対応する部位以外に設けられていることを特徴とするものである。
【０００７】
【発明の実施の形態】
以下、本発明の実施の形態について、添付図面を参照しながら説明する。
実施の形態１．
図１は、本発明の実施の形態１に係る電力用半導体装置の内部構造を示す縦断面説明図である。この電力用半導体装置１０は、基本的に、制御基板２を含む制御部（図中の上段側の構成）と、電力用半導体素子９を搭載した絶縁基板６を含むパワー部（図中の下段側の構成）とから構成されている。制御部に含まれる制御基板２は、装置本体の外形を構成する樹脂ケース４内に規定された空間部５に保持され、その制御基板２上には、抵抗，コンデンサ，制御用ＩＣ等の部品３が搭載されている。他方、パワー部に含まれる絶縁基板６は、装置本体の底面を構成する金属製のベース板１１上に放熱および位置固定のために取り付けられ、その絶縁基板６上には、複数（この実施の形態では２つ）の電力用半導体素子９が搭載されている。
【０００８】
制御基板２と絶縁基板６とは、中継端子１１を介して電気的に接続され、電力用半導体素子９のスイッチング動作によって、絶縁基板６側から制御基板２側へ供給される電力が変換・制御されるようになっている。
【０００９】
樹脂ケース４は、ケース成形時にインサート成形された複数の主回路端子１６を有しており、各主回路端子１６は、その一部でケース４の外面に露出して、装置１０の外部端子を構成している。また、樹脂ケース４内には、制御基板２および絶縁基板６を収納する空間部５が規定されている。この空間部５は、ケース４の上面側で、蓋１８が取り付けられることにより閉じられ、他方、ケース４の下面側では、樹脂ケース４がその下端部にてベース板１１に接合されることにより閉じられる。なお、蓋１８には開口部１８ａが設けられ、この開口部１８ａを介して、信号回路用コネクタ１７が制御基板２に装着されるようになっている。
【００１０】
電力用半導体素子９が搭載される絶縁基板６の表面側には、半導体素子搭載用の回路パターン７（以下、表面パターンと称す）が形成され、他方、絶縁基板６の裏面側には、金属パターン８（以下、裏面パターンと称す）が形成されている。なお、図１において、表面パターン７は、べた一面に広がるように示されるが、平面視した場合には、搭載される半導体素子９用の電極や配線を構成する形状を有するものである。
【００１１】
表面パターン７上の所定位置には、電力用半導体素子９が、ハンダ１２を用いて接合されている。そして、絶縁基板６は、裏面パターン８が形成された側で、ハンダ層１３を介してベース板１１に接合されている。また、半導体素子９ともう一方の半導体素子９との間，半導体素子９と中継端子１５との間、および、半導体素子９と主回路端子１６との間が、アルミワイヤ１４で電気的に接続されている。このように、絶縁基板６がベース板１１にハンダ接合され、各構成要素間がアルミワイヤ１４で接続された状態で、絶縁基板６及びアルミワイヤ１４は、図１に示すように、樹脂ケース４内に規定される空間部５の下半分に充填されたシリコンゲル１９によって封止される。
【００１２】
この実施の形態１では、絶縁基板６の裏面側に形成された裏面パターン８が、その中央部に、切欠き部８ａを備えている。この中央部は、絶縁基板６の表面側に搭載される２つの電力用半導体素子９間の空き領域（半導体素子９が存在しない領域）に対応する部位である。また、ハンダ層１３には、切欠き部８ａに対応する部位にて、孔部１３ａが形成されている。
【００１３】
このように、裏面パターン８に切欠き部８ａが形成されることにより、電力用半導体素子９のスイッチング動作時に発生する熱によって裏面パターン８とベース板１１との間のハンダ層１３に生じる応力を緩和することができ、ハンダ層１３にクラックが発生する惧れをなくすることができる。また、この実施の形態１では、切欠き部８ａが絶縁基板６の表面側に搭載される２つの半導体素子９間の空き領域に対応して設けられ、各半導体素子９に対応する部位にて裏面パターン８は存在するため、放熱効果は十分に確保される。
【００１４】
なお、この実施の形態１では、絶縁基板６上に２つの半導体素子９が設けられる場合について説明したが、これに限定されることはなく、例えば、３つの半導体素子９が絶縁基板６上で所定の間隔を隔てて搭載されている場合には、切欠き部８ａを、それらの半導体素子９間の２つの空き領域に対応して設けることにより、上記と同様の効果を得ることができる。また、特に図示しないが、ハンダ層１３におけるクラック発生をより確実に防止するには、切欠き部８ａが、絶縁基板６の表面側での半導体素子９間の空き領域に対応する部位のみならず、半導体素子９が搭載される領域に対応する部位に形成されてもよい。
【００１５】
以下、本発明の別の実施の形態について説明する。なお、以下では、上記実施の形態１における場合と同じものについては同一の符号を付し、それ以上の説明を省略する。
実施の形態２．
図２は、本発明の実施の形態２に係る電力用半導体装置に組み込まれる絶縁基板およびその裏面パターンを示す平面図である。裏面パターン２３は、絶縁基板６の形状に対応して、矩形状に形成されている。この裏面パターン２３には、その中央に、すなわち、絶縁基板６の表面側に搭載される２つの電力用半導体素子９間の空き領域に対応する部位にて、矩形状の切欠き部２３ａが形成されている。更に、この裏面パターン２３には、４つのコーナ部を含む周縁部に、円形状の切欠き部２３ｂが所定の間隔を隔てて複数形成されている。
【００１６】
この実施の形態２では、裏面パターン２３の中央に形成される切欠き部２３ａが設けられることにより、上記実施の形態１における場合と同様の効果が得られるとともに、、裏面パターン２３の４つのコーナ部を含む周縁部に形成される切欠き部２３ｂが設けられることにより、裏面パターン２３とベース板１１（図１参照）との間のハンダ層８に生じる応力を一層緩和することができ、ハンダ層１３におけるクラック発生を一層確実に防止することができる。
【００１７】
なお、切欠き部２３ｂは、裏面パターン２３の４つのコーナ部を含む周縁部に限定されることなく、少なくとも４つのコーナ部に形成されればよい。また、切欠き部２３ｂの形状は、円形状に限定されるものでなく、ハンダ層８に生じる応力を緩和することができれば、いかなる形状であってもよい。
【００１８】
実施の形態３．
図３は、本発明の実施の形態３に係る電力用半導体装置の内部構造の一部を拡大して示す縦断面説明図である。この実施の形態３では、絶縁基板６の表面側に搭載された電力用半導体素子９の占める領域に基づき規定される部位に、裏面パターン３３が形成されている。この部位は、図３から分かるように、絶縁基板６の表面側における半導体素子９の下端部と絶縁基板６との接線を通過し、基板平面と角度θ（θ＜９０°）をなす平面によって規定される内側領域Ａ１及びＡ２に含まれる部位である。かかる部位の設定条件によれば、半導体素子９が搭載された領域に対応する部位及びその近傍に裏面パターン３３が形成されることになる。また、これを言い換えれば、半導体素子９が搭載された領域に対応する部位及びその近傍以外に、切欠き部３３ａ及び３３ｂが形成されることになる。
【００１９】
このように、裏面パターン３３に切欠き部３３ａ及び３３ｂが形成されることにより、電力用半導体素子９のスイッチング動作時に発生する熱によって裏面パターン３３とベース板１１との間のハンダ層１３に生じる応力を緩和することができ、ハンダ層１３にクラックが発生する惧れをなくすることができる。また、この実施の形態３によれば、切欠き部３３ａ及び３３ｂが、半導体素子９が搭載された領域に対応する部位及びその近傍以外に形成されることにより、各半導体素子９に対応する部位及びその近傍にて裏面パターン３３は存在するため、放熱効果は十分に確保される。
【００２０】
なお、本発明は、例示された実施の形態に限定されるものでなく、本発明の要旨を逸脱しない範囲において、種々の改良及び設計上の変更が可能であることは言うまでもない。
【００２１】
【発明の効果】
以上の説明から明らかなように、本願の第１の発明によれば、その表面側で回路パターンが形成された上で電力用半導体素子が搭載される一方、その裏面側では金属パターンが形成された上でハンダ層を介して放熱および位置固定用のベース板に接合される絶縁基板を備えた電力用半導体装置において、上記絶縁基板の裏面側に形成される金属パターンの所定部位に、切欠き部が設けられているので、簡単な構成で、裏面パターンとベース板との間のハンダ層に生ずる応力を緩和することができ、その結果、ハンダ層におけるクラック発生による放熱性の低下を有効に防止することができる。
【００２２】
また、本願の第２の発明によれば、上記切欠き部が、上記金属パターンにおける、上記絶縁基板の表面側で電力用半導体素子が搭載される領域に対応する部位以外に設けられているので、放熱効果を確保しつつ、簡単な構成で、裏面パターンとベース板とのハンダ層に生ずる応力を抑制することができる。
【００２３】
更に、上記金属パターンが矩形状に形成されており、上記切欠き部が、更に、該金属パターンにおけるコーナ部に設けられているので、簡単な構成で、裏面パターンとベース板とのハンダ層に生ずる応力を一層緩和することができ、その結果、ハンダ層におけるクラック発生による放熱性の低下を有効に防止することができる。
【図面の簡単な説明】
【図１】 本発明の実施の形態１に係る電力用半導体装置の内部構造をあらわす縦断面説明図である。
【図２】 本発明の実施の形態２に係る電力用半導体装置に組み込まれる絶縁基板の裏面一体金属パターンを示す平面図である。
【図３】 本発明の実施の形態３に係る電力用半導体装置の内部構造の一部（ベース板に対する絶縁基板の接合構造）を拡大して示す縦断面説明図である。
【図４】 従来の電力用半導体装置の内部構造を示す縦断面説明図である。
【符号の説明】
６ 絶縁基板，７ 回路パターン，８，２３，３３ 裏面パターン，８ａ，２３ａ，２３ｂ，３３ａ，３３ｂ 切欠き部，９ 電力用半導体素子，１０ 電力用半導体装置，１１ ベース板，１２ ハンダ，１３ ハンダ層。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a power semiconductor device such as an inverter, and more particularly to a structure for fixing an insulating substrate mounted with a power semiconductor element in the device to a base plate.
[0002]
[Prior art]
Conventionally, in a power semiconductor device, an insulating substrate on which a power semiconductor element is mounted is generally soldered to a base plate because of the necessity of heat dissipation and position fixing. FIG. 4 shows an example of an internal structure of a conventionally known power semiconductor device. In the power semiconductor device 50, a circuit pattern 53 (hereinafter referred to as a surface pattern) for mounting a semiconductor element is formed on the surface side of the insulating substrate 52 on which the power semiconductor element 51 is mounted. A metal pattern 54 (hereinafter referred to as a back surface pattern) is formed on the back surface side of the metal pattern 54 so as to extend over substantially the entire surface.
On the surface pattern 53, the power semiconductor element 51 is bonded using the solder 55. The insulating substrate 52 is bonded to the metal base plate 59 via a solder layer 56 extending over the entire surface of the back surface pattern 54 on the back surface side.
[0003]
[Problems to be solved by the invention]
However, in such a power semiconductor device 50, the insulating substrate 52 and the base plate 59 are thermally expanded by heat generated during the switching operation of the power semiconductor element 51, so that cracks are generated in the solder layer 56 that joins the two. There is a possibility that it will occur. This crack becomes a factor which causes destruction of each element and insulation failure due to a decrease in heat dissipation.
[0004]
The present invention has been made in view of the above technical problem, and provides a power semiconductor device that can reliably prevent generation of cracks in a solder layer that joins an insulating substrate on which a power semiconductor element is mounted and a base plate. The purpose is to provide.
[0005]
[Means for Solving the Problems]
In the first invention of the present application, the power semiconductor element is mounted after the circuit pattern is formed on the front surface side, while the heat radiation and the position are provided via the solder layer after the metal pattern is formed on the back surface side. In a power semiconductor device including an insulating substrate bonded to a fixing base plate, the metal pattern is rectangular, and a notch is provided in a corner portion of the metal pattern. .
[0006]
The second invention of the present application is further characterized in that the notch is provided in a portion other than the portion corresponding to the region where the power semiconductor element is mounted on the surface side of the insulating substrate in the metal pattern. To do.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
Embodiment 1 FIG.
FIG. 1 is a longitudinal cross-sectional explanatory view showing the internal structure of the power semiconductor device according to the first embodiment of the present invention. This power semiconductor device 10 basically includes a control unit including the control board 2 (upper side configuration in the figure) and a power unit including the insulating substrate 6 on which the power semiconductor element 9 is mounted (lower stage in the figure). Side structure). The control board 2 included in the control unit is held in a space part 5 defined in a resin case 4 constituting the outer shape of the apparatus main body. On the control board 2, components such as a resistor, a capacitor, and a control IC are provided. 3 is installed. On the other hand, the insulating substrate 6 included in the power unit is attached on a metal base plate 11 constituting the bottom surface of the apparatus main body for heat dissipation and position fixing, and a plurality of (this embodiment) is mounted on the insulating substrate 6. In the embodiment, two power semiconductor elements 9 are mounted.
[0008]
The control board 2 and the insulating board 6 are electrically connected via the relay terminal 11, and the power supplied from the insulating board 6 side to the control board 2 side is converted and controlled by the switching operation of the power semiconductor element 9. It has come to be.
[0009]
The resin case 4 has a plurality of main circuit terminals 16 that are insert-molded at the time of molding the case. Each main circuit terminal 16 is partially exposed to the outer surface of the case 4 so that the external terminals of the device 10 can be used. It is composed. In the resin case 4, a space 5 for accommodating the control board 2 and the insulating board 6 is defined. The space portion 5 is closed by attaching a lid 18 on the upper surface side of the case 4, and on the other hand, on the lower surface side of the case 4, the resin case 4 is joined to the base plate 11 at the lower end portion thereof. Closed. The lid 18 is provided with an opening 18a, and the signal circuit connector 17 is attached to the control board 2 through the opening 18a.
[0010]
A circuit pattern 7 for mounting a semiconductor element (hereinafter referred to as a surface pattern) is formed on the surface side of the insulating substrate 6 on which the power semiconductor element 9 is mounted, while a metal pattern is formed on the back side of the insulating substrate 6. A pattern 8 (hereinafter referred to as a back surface pattern) is formed. In FIG. 1, the surface pattern 7 is shown so as to spread over the entire surface. However, when viewed in plan, the surface pattern 7 has a shape constituting an electrode or wiring for the semiconductor element 9 to be mounted.
[0011]
A power semiconductor element 9 is bonded to a predetermined position on the surface pattern 7 using solder 12. The insulating substrate 6 is bonded to the base plate 11 via the solder layer 13 on the side where the back surface pattern 8 is formed. Also, the aluminum wire 14 is electrically connected between the semiconductor element 9 and the other semiconductor element 9, between the semiconductor element 9 and the relay terminal 15, and between the semiconductor element 9 and the main circuit terminal 16. Has been. In this manner, the insulating substrate 6 and the aluminum wire 14 are connected to the resin case 4 as shown in FIG. 1 in a state where the insulating substrate 6 is soldered to the base plate 11 and the components are connected by the aluminum wires 14. It is sealed by the silicon gel 19 filled in the lower half of the space 5 defined inside.
[0012]
In the first embodiment, the back surface pattern 8 formed on the back surface side of the insulating substrate 6 has a notch 8a at the center. This central portion is a portion corresponding to a vacant region between the two power semiconductor elements 9 mounted on the surface side of the insulating substrate 6 (a region where the semiconductor element 9 does not exist). In addition, a hole 13a is formed in the solder layer 13 at a site corresponding to the notch 8a.
[0013]
Thus, by forming the notch 8a in the back surface pattern 8, the stress generated in the solder layer 13 between the back surface pattern 8 and the base plate 11 due to heat generated during the switching operation of the power semiconductor element 9 is caused. This can alleviate and eliminate the possibility of cracks occurring in the solder layer 13. Further, in the first embodiment, the notch 8 a is provided corresponding to the empty area between the two semiconductor elements 9 mounted on the surface side of the insulating substrate 6, and at a portion corresponding to each semiconductor element 9. Since the back surface pattern 8 exists, the heat dissipation effect is sufficiently ensured.
[0014]
In the first embodiment, the case where two semiconductor elements 9 are provided on the insulating substrate 6 has been described. However, the present invention is not limited to this. For example, three semiconductor elements 9 are provided on the insulating substrate 6. In the case where they are mounted at a predetermined interval, the same effect as described above can be obtained by providing the notches 8 a corresponding to the two empty regions between the semiconductor elements 9. Although not particularly illustrated, in order to prevent cracks in the solder layer 13 more reliably, the notch 8a is not only a part corresponding to the empty area between the semiconductor elements 9 on the surface side of the insulating substrate 6. The semiconductor element 9 may be formed in a part corresponding to the region where the semiconductor element 9 is mounted.
[0015]
Hereinafter, another embodiment of the present invention will be described. In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and further description thereof is omitted.
Embodiment 2. FIG.
FIG. 2 is a plan view showing an insulating substrate and its back surface pattern incorporated in the power semiconductor device according to the second embodiment of the present invention. The back surface pattern 23 is formed in a rectangular shape corresponding to the shape of the insulating substrate 6. The back surface pattern 23 is formed with a rectangular cutout portion 23a at the center thereof, that is, at a portion corresponding to an empty area between the two power semiconductor elements 9 mounted on the front surface side of the insulating substrate 6. Has been. Furthermore, a plurality of circular notches 23b are formed on the back surface pattern 23 at predetermined intervals on the peripheral edge including the four corners.
[0016]
In the second embodiment, by providing the notch portion 23a formed at the center of the back surface pattern 23, the same effect as in the case of the first embodiment can be obtained, and the four corners of the back surface pattern 23 can be obtained. By providing the notch portion 23b formed in the peripheral portion including the portion, the stress generated in the solder layer 8 between the back surface pattern 23 and the base plate 11 (see FIG. 1) can be further alleviated, and the solder Generation of cracks in the layer 13 can be more reliably prevented.
[0017]
In addition, the notch part 23b is not limited to the peripheral part containing the four corner parts of the back surface pattern 23, What is necessary is just to be formed in at least four corner parts. Moreover, the shape of the notch 23b is not limited to a circular shape, and may be any shape as long as the stress generated in the solder layer 8 can be relieved.
[0018]
Embodiment 3 FIG.
FIG. 3 is an explanatory longitudinal sectional view showing a part of the internal structure of the power semiconductor device according to the third embodiment of the present invention. In the third embodiment, the back surface pattern 33 is formed at a site defined based on a region occupied by the power semiconductor element 9 mounted on the front surface side of the insulating substrate 6. As can be seen from FIG. 3, this portion passes through a tangent line between the lower end portion of the semiconductor element 9 on the surface side of the insulating substrate 6 and the insulating substrate 6 and is formed by a plane that forms an angle θ (θ <90 °) with the substrate plane. it is a site contained in the inner area a 1 and a 2 are defined. According to the setting conditions of such a part, the back surface pattern 33 is formed in the part corresponding to the region where the semiconductor element 9 is mounted and in the vicinity thereof. In other words, the notches 33a and 33b are formed in addition to the portion corresponding to the region where the semiconductor element 9 is mounted and the vicinity thereof.
[0019]
Thus, by forming the notches 33 a and 33 b in the back surface pattern 33, heat is generated during the switching operation of the power semiconductor element 9 and is generated in the solder layer 13 between the back surface pattern 33 and the base plate 11. The stress can be relaxed, and the possibility of cracks occurring in the solder layer 13 can be eliminated. Further, according to the third embodiment, the notches 33a and 33b are formed in portions other than the portion corresponding to the region where the semiconductor element 9 is mounted and the vicinity thereof, thereby the portion corresponding to each semiconductor element 9 And since the back surface pattern 33 exists in the vicinity thereof, a sufficient heat dissipation effect is secured.
[0020]
Note that the present invention is not limited to the illustrated embodiments, and it goes without saying that various improvements and design changes are possible without departing from the scope of the present invention.
[0021]
【The invention's effect】
As is clear from the above description, according to the first invention of the present application, the power semiconductor element is mounted after the circuit pattern is formed on the front surface side, while the metal pattern is formed on the back surface side. In addition, in a power semiconductor device including an insulating substrate bonded to a base plate for heat dissipation and position fixing via a solder layer, a notch is formed in a predetermined portion of the metal pattern formed on the back side of the insulating substrate. Since the part is provided, the stress generated in the solder layer between the back surface pattern and the base plate can be relieved with a simple configuration, and as a result, the heat dissipation is effectively reduced due to the occurrence of cracks in the solder layer. Can be prevented.
[0022]
According to the second invention of the present application, the notch is provided in a portion other than the portion corresponding to the region where the power semiconductor element is mounted on the surface side of the insulating substrate in the metal pattern. The stress generated in the solder layer between the back surface pattern and the base plate can be suppressed with a simple configuration while ensuring the heat dissipation effect.
[0023]
Further, the metal pattern is formed in a rectangular shape, and the notch is further provided in a corner portion of the metal pattern, so that the solder layer between the back pattern and the base plate can be formed with a simple configuration. The resulting stress can be further relaxed, and as a result, a reduction in heat dissipation due to the occurrence of cracks in the solder layer can be effectively prevented.
[Brief description of the drawings]
FIG. 1 is a longitudinal sectional view illustrating an internal structure of a power semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a plan view showing a back surface integrated metal pattern of an insulating substrate incorporated in a power semiconductor device according to a second embodiment of the present invention.
FIG. 3 is an explanatory longitudinal sectional view showing a part of the internal structure of a power semiconductor device according to a third embodiment of the present invention (bonding structure of an insulating substrate to a base plate).
FIG. 4 is a longitudinal sectional view showing an internal structure of a conventional power semiconductor device.
[Explanation of symbols]
6 Insulating substrate, 7 Circuit pattern, 8, 23, 33 Back surface pattern, 8a, 23a, 23b, 33a, 33b Notch, 9 Power semiconductor element, 10 Power semiconductor device, 11 Base plate, 12 Solder, 13 Solder layer.

Claims (2)

その表面側で回路パターンが形成された上で電力用半導体素子が搭載される一方、その裏面側では金属パターンが形成された上でハンダ層を介して放熱および位置固定用のベース板に接合される絶縁基板を備えた電力用半導体装置において、
上記金属パターンが矩形状であり、上記金属パターンのコーナ部に切欠き部が設けられていることを特徴とする電力用半導体装置。A power semiconductor element is mounted after a circuit pattern is formed on the front side, and a metal pattern is formed on the back side and bonded to a base plate for heat dissipation and position fixing via a solder layer. In a power semiconductor device including an insulating substrate,
The power semiconductor device according to claim 1, wherein the metal pattern has a rectangular shape, and a corner portion of the metal pattern is provided with a notch. 更に、上記切欠き部が、上記金属パターンにおける、上記絶縁基板の表面側で電力用半導体素子が搭載される領域に対応する部位以外に設けられていることを特徴とする請求項１記載の電力用半導体装置。 2. The electric power according to claim 1 , wherein the notch is provided in a portion other than a portion of the metal pattern corresponding to a region where the power semiconductor element is mounted on the surface side of the insulating substrate. Semiconductor device.
JP2001241952A 2001-08-09 2001-08-09 Power semiconductor device Expired - Lifetime JP4330293B2 (en)

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