JPS63283044A - 半導体集積回路装置 - Google Patents

半導体集積回路装置

Info

Publication number
JPS63283044A
JPS63283044A JP62118460A JP11846087A JPS63283044A JP S63283044 A JPS63283044 A JP S63283044A JP 62118460 A JP62118460 A JP 62118460A JP 11846087 A JP11846087 A JP 11846087A JP S63283044 A JPS63283044 A JP S63283044A
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit device
film
semiconductor integrated
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62118460A
Other languages
English (en)
Inventor
Masahiro Takagi
正博 高木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62118460A priority Critical patent/JPS63283044A/ja
Publication of JPS63283044A publication Critical patent/JPS63283044A/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05639—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は高速メモリのα線対策としてポリイミ■・樹脂
膜等の有機物を被膜した半導体集積回路装置に関し、特
にその電極構造を改善した半導体集積回路装置に関する
。
〔従来の技術〕
近年の半導体集積回路の微細化および高速化に伴って、
特に高速メモリ系のα線による誤動作防止対策の必要性
か高まっている。
第３図はかかる従来の一例を説明するための半導体集積
回路装置の断面図である。
第３図に示すように、かかる装置の構造、特に電極構造
はパッド１３により形成され、この電極とリードフレー
ムをボンデインクした後、ポリイミド樹脂を被膜する構
造となっている。
かかる工程を詳細に説明すると、まづ半導体基板１１の
主表面上に絶縁膜２を被覆し、その絶縁膜１２上にアル
ミニウムのパット１３を被着形成する。次に、この絶縁
膜１２上全面を保護膜１４て覆い、パットＸ３の上の所
定の位置を開孔する。かかる半導体基板１１等からなる
ペレットをケース１７に固着し、しかる後ケース１７の
別の個所に位置するリードフレーム１８とパッド１３と
の間をボンディクワイヤー１９によりボンティング接続
する。次に、ペレット全面にα線対策としてのポリイミ
ド樹脂膜２０を被覆して装置として仕上げている。
〔発明が解決しようとする問題点〕
上述した従来の電極構造を有する半導体集積回路装置に
おいては、ホンティング接続後半導体基板上全面にポリ
イミドを被膜すると、ホンティグワイヤーにまでこのポ
リイミド膜がかかってしまう。従って、かかるポリイミ
ドをキュアーし、且つガス抜きする時そのポリイミド樹
脂の収縮応力によりワイヤーがペレット中央方向に引っ
ばられ、ワイヤー形状の変形、更にはボンディング電極
部ネック切れなどを引き起すという欠点かある。
本発明の目的は、かかるボンティクワイヤー形状の変形
やボンディング電極部ネック切れなどを防止する半導体
集積回路装置を提供することにある。
〔問題点を解決するための手段〕
本発明の半導体集積回路装置は、半導体基板の主表面に
絶縁膜を介して被着したパッドと、このパッド上に形成
した突起電極部くバンプ）と、この電極部にホンディン
グ接続されるリードフレームと、α線による誤動作防止
のためにペレット表面に被覆した有機膜とを含んで構成
される。
〔実施例〕
次に、本発明の実施例について図面を参照して説明する
。
第１図は本発明の第一の実施例を説明するための半導体
集積回路装置の断面図である。
第１図に示すように、半導体基板１の主表面を絶縁膜２
で覆い、その絶縁膜２上にアルミニウムのパッド３を設
ける。次に、パッド３を含む半導体基板上全面を保護膜
４で覆い、しかる後パット３旧の外周部を除く所定の位
置を開孔し、その開孔部上にＣｕバンプ５を形成する。
次に、このバンプ５の上面にＡｇメツキロを施す。次に
、かかるハンプ構造を有するペレットをケース７にマウ
ントし、バンプ５のＡｇメッキ部６とケース７の別の位
置に設けられたリードフレーム８とをホンディングワイ
ヤー９により接続する。最後に、α線対策の有機膜とし
てポリイミド樹脂膜１０をペレット全面に被覆形成して
装置として仕上げる。
かかる電極構造を有する集積回路装置によれば、ポリイ
ミド樹脂膜１０かポンチインクワイヤー９にかかること
がなく、ポリイミド樹脂膜１０の収縮による影響を受け
ないて済む。
第２図は本発明の第二の実施例を説明するための半導体
集積回路装置の断面図である。
第２図に示すように、半導体基板１上に絶縁膜２、パッ
ド３を形成し、この上に全面保護膜４て覆うことまでは
前述した第一の実施例と同しである。この第二の実施例
においては、保護膜４の所定の位置に形成した開孔部に
、鉛と錫の合金、または鉛とインジウムの合金等の半田
付は材料を用いて半田バンプ５を形成する。次に、本構
造のペレットをケース７にマウントし、長く伸びている
リードフレーム８の先端とハンプ部５とを加熱に〜５− より融着させて接続する。この場合、α線対策としてシ
リコーン系の低温処理の可能な有機物１０ｂを被膜とす
ることが望ましい。
〔発明の効果〕
以上説明したように、本発明は半導体集積回路装置の電
極構造をバットたけてなくその上にバンプを形成する構
造にすることにより、ポリイミド等のα線対策に施した
有機物の被膜の収縮によってもボディングワイヤーおよ
び電極部が何ら影響されることなく、したかって高信頼
性且つ高歩留りの製品を得られるという効果がある。
【図面の簡単な説明】
第１図は本発明の第一の実施例を説明するための半導体
集積回路装置の断面図、第２図は本発明の第二の実施例
を説明するための半導体集積回路装置の断面図、第３図
は従来の一例を説明するための同様装置の断面図である
。 １・・・半導体基板、２・・・絶縁膜、３・・・アルミ
ニウムバット、４・・・保護膜、５・・・バンプ、６・
・・Ａｇメー　６　＝ ツキ、７・・ケース、８・・・リードフレーム、９・・
ホンティングワイヤー、１０ａ・・・ポリイミド樹脂膜
、１０ｂ・・・シリコーン膜。

Claims (1)

  1. 【特許請求の範囲】 １、半導体基板の主表面に絶縁膜を介して被着したパッ
    ドと、このパッド上に形成した突起電極部と、この電極
    部にボンディング接続されるリードフレームと、α線に
    よる誤動作防止のためにペレット表面に被覆した有機膜
    とを含むことを特徴とする半導体集積回路装置。 ２、有機膜をポリイミド樹脂膜で形成した特許請求の範
    囲第１項記載の半導体集積回路装置。 ３、有機膜をシリコーン系樹脂膜で形成した特許請求の
    範囲第１項記載の半導体集積回路装置。
JP62118460A 1987-05-14 1987-05-14 半導体集積回路装置 Pending JPS63283044A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62118460A JPS63283044A (ja) 1987-05-14 1987-05-14 半導体集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62118460A JPS63283044A (ja) 1987-05-14 1987-05-14 半導体集積回路装置

Publications (1)

Publication Number Publication Date
JPS63283044A true JPS63283044A (ja) 1988-11-18

Family

ID=14737201

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62118460A Pending JPS63283044A (ja) 1987-05-14 1987-05-14 半導体集積回路装置

Country Status (1)

Country Link
JP (1) JPS63283044A (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000057472A1 (de) * 1999-03-24 2000-09-28 Infineon Technologies Ag Verfahren zum verbinden eines anschlussdrahtes mit einem anschlusskontakt eines integrierten schaltkreises
US6774499B1 (en) * 2003-04-02 2004-08-10 Siliconware Precision Industries Co., Ltd. Non-leaded semiconductor package and method of fabricating the same
US6927156B2 (en) * 2003-06-18 2005-08-09 Intel Corporation Apparatus and method extending flip-chip pad structures for wirebonding on low-k dielectric silicon

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000057472A1 (de) * 1999-03-24 2000-09-28 Infineon Technologies Ag Verfahren zum verbinden eines anschlussdrahtes mit einem anschlusskontakt eines integrierten schaltkreises
US6774499B1 (en) * 2003-04-02 2004-08-10 Siliconware Precision Industries Co., Ltd. Non-leaded semiconductor package and method of fabricating the same
US6927156B2 (en) * 2003-06-18 2005-08-09 Intel Corporation Apparatus and method extending flip-chip pad structures for wirebonding on low-k dielectric silicon
US7262513B2 (en) 2003-06-18 2007-08-28 Intel Corporation Apparatus and method extending flip-chip pad structures for wirebonding on low-k dielectric silicon

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