JPS6322464B2 - - Google Patents

Info

Publication number
JPS6322464B2
JPS6322464B2 JP55182010A JP18201080A JPS6322464B2 JP S6322464 B2 JPS6322464 B2 JP S6322464B2 JP 55182010 A JP55182010 A JP 55182010A JP 18201080 A JP18201080 A JP 18201080A JP S6322464 B2 JPS6322464 B2 JP S6322464B2
Authority
JP
Japan
Prior art keywords
wiring
film
layer
forming
bonding pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55182010A
Other languages
English (en)
Other versions
JPS57106140A (en
Inventor
Keiji Myamoto
Tooru Kawanobe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP55182010A priority Critical patent/JPS57106140A/ja
Publication of JPS57106140A publication Critical patent/JPS57106140A/ja
Publication of JPS6322464B2 publication Critical patent/JPS6322464B2/ja
Granted legal-status Critical Current

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Classifications

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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]

Description

【発明の詳細な説明】 本発明はIC，LSI等のごとき半導体装置におけ
る電極部構成技術に関する。
IC，LSIにおいては、Si等の半導体基板チツプ
の表面にトランジスタやダイオード等の能動素子
領域を形成し、素子の電極としてAl配線を導出
してその外端子をボンデイングパツドとして能動
領域を避けたチツプ周辺部に配列した構造を有す
る。最近のようにICの微細化が進み素子が高集
積化してくるとボンデイングパツドのチツプ上に
占める面積比が増大しチツプの価格増大につなが
ることになつた。
本願出願人においてはボンデイングパツドをチ
ツプ周辺部に限らず能動領域上の保護絶縁膜の上
を利用し、この上にボンデイングパツドを設ける
ようにすればチツプ面積はそれだけ小さくてすむ
ことを考え、その実現を図つている。このような
電極構造とするためには、能動領域上のボンデイ
ングパツドまで配線を形成しなければならない。
この配線には通常Au（金）又はAl（アルミニウ
ム）が考えられるが、Auは高価であること、Al
の場合は腐食され易いという問題がある。
本発明は上記した問題を解決するためなされた
ものであり、その目的はAu又はAl配線に代る配
線でAu，Alのワイヤボンデイングが可能な電極
をもち、かつ耐食性にすぐれた配線構成の提供に
ある。
本発明の他の目的は、前記目的を達成するため
の製造工程を低減することにある。
以下本発明を半導体装置の配線形成プロセスを
示す第１図ａ〜ｇに従つて詳細に説明する。
(a) Si半導体基板１の一主面表面に公知の選択的
不純物拡散技術によつて半導体素子領域２を形
成し、表面を酸化膜３で覆い、コンタクト部４
を窓開したものを用意する。
(b) 素子領域のコンタクト部に接続し、酸化膜３
上に延在するAl配線５を第１の配線として形
成する。
(c) Al配線の上を覆う第１の絶縁膜であるPSG
（リンシリケートガラス）膜６を基板全面に形
成し、PSG膜６の一部にスルーホール７を窓
開してAl配線５の一部を露出する。
(d) PSG膜６の全面に膜厚1000〜2000ÅのTi（チ
タン）及び膜厚１〜2μmのCu（銅）をスパツタ
リング又は蒸着し、第２の配線となるTi層８
及びCu層９（第２の配線形成層）を形成する。
このとき、Ti層８の一部は、スルーホール７
を通してAl配線５に接続される。次いでCu層
９上の全面にパツシベイシヨン膜（保護絶縁
膜）１０としてポリイミド系樹脂膜例えばポリ
イミド・イソ・インドロキナゾリンジオン膜を
回転塗布法により２〜4μm厚に形成する。
(e) ホトレジスト処理により、上記ポリイミド系
樹脂１０を例えばヒドラジン等によりパターニ
ングエツチする。このときのポリイミド系樹脂
のパターンは同図e′に符号１０を付けて示すよ
うに、Al配線５との接続部分から能動領域上
に引出し延在する第２の配線の形成領域を覆
い、かつ第２の配線の形成領域内にボンデイン
グパツドの形成領域となる開口部を有するよう
に構成される。つまり、ポリイミド系樹脂は、
第２の配線とボンデイングパツドとを形成する
マスク１０となる。
(f) 前記開口部以外のマスク１０とオーバラツプ
するホトレジスト膜１１を形成し、ボンデイン
グパツドとなる部分のCu膜の表面に電気めつ
き法により電極形成用金属層としてまずNi（ニ
ツケル）膜１２を形成し、次いでAu（金）膜１
３を被着する。この電極形成用金属層の形成に
よつて、ボンデイングパツドを形成することが
できる。
(g) ホトレジストを除去し、Au膜及びポリイミ
ド系樹脂膜をマスクとして周辺のCu膜及びTi
膜を電解エツチ除去することによりワイヤボン
デイングパツド及び第２の配線が完成する。
第２図ａ，ｂは完成した半導体装置の電極にお
いて、ボンデイングパツド部１２にAuワイヤ１
３をボンデイングした場合の形態を示す。
以上実施例で述べた本発明によれば、(1)第２の
配線として下層にAl及び絶縁膜（PSG）に対し
て接合性の良いTi層８を、上層に耐食性がよく
導電性の良いCu層９を使用し、かつボンデイン
グ面にはCuと接合性の良いNi膜１１を介してAu
やAlのワイヤボンデイングが可能なAu膜１２を
形成したものであつて、ワイヤボンデイングが可
能なこと、Auを部分的に設けることで価格上ほ
とんど問題とならないこと、又、第２配線の表面
はポリイミド系樹脂膜１０で保護的に覆つてある
こと、さらにこのポリイミド系樹脂膜をそのまま
Cu―Ti膜のエツチングマスクに使用するため工
程数が低減できること等前記発明の目的を達成で
きる。
本発明は前記実施例に限定されない。
例えば第２の配線としてTi―Cuの代りにTi―
Niを使用することもできる。又、ポリイミド系
樹脂に代えてSi3N4（窒化シリコン）を用いても
良い。
【図面の簡単な説明】
第１図ａ〜ｇは本発明による半導体装置の電極
構成のプロセスを示す工程断面図であり、同図
e′はｅに対応する上面図である。第２図ａは本発
明による半導体装置の完成時の断面図、同図ｂは
ａに対応する上面図である。 １……Si基板、２……素子領域、３……表面酸
化膜、４……コンタクト部、５……Al配線、６
……PSG膜、７……スルーホール、８……Ti膜、
９……Cu膜、１０……ポリイミド系樹脂膜、１
１……Ni膜、１２……Au膜、１３……ワイヤ。

Claims (1)

  1. 【特許請求の範囲】 １ 半導体基板表面の能動領域に接続された第１
    の配線を設け、該第１の配線に接続しかつ前記能
    動領域上に引き出し延在する、前記第１の配線の
    上層に形成された耐食性を有する第２の配線を設
    け、該第２の配線の引き出された一部分に電極形
    成用金属層を積層したボンデイングパツドを設け
    たことを特徴とする半導体装置。 ２ 前記第１の配線はAlで構成し、前記第２の
    配線は下層をTi上層をCuで構成したことを特徴
    とする特許請求の範囲第１項に記載の半導体装
    置。 ３ 前記ボンデイングパツドの電極形成用金属層
    は、下層をNi上層をAuで構成したことを特徴と
    する特許請求の範囲第１項又は第２項に記載の半
    導体装置。 ４ 半導体基板表面の能動領域に接続された第１
    の配線を形成する工程と、該第１の配線を覆う絶
    縁膜を基板全面に形成する工程と、該絶縁膜の前
    記第１の配線の所定上部を選択的に除去してスル
    ーホールを形成する工程と、該スルーホールを通
    して前記第１の配線に接続しかつ前記絶縁膜上全
    面に形成された耐食性を有する第２の配線形成層
    を形成する工程と、該第２の配線形成層の上部
    に、前記第１の配線との接続部分から前記能動領
    域上に引き出し延在する第２の配線の形成領域を
    覆い、かつ第２の配線の形成領域内にボンデイン
    グパツドの形成領域となる開口部を有するマスク
    を形成する工程と、該マスクの開口部から露出す
    る第２の配線形成層上に電極形成用金属層を積層
    してボンデイングパツドを形成する工程と、該ボ
    ンデイングパツド及び前記マスクを用いて、それ
    以外の領域の前記第２の配線形成層を除去して第
    ２の配線を形成する工程とを備えたことを特徴と
    する半導体装置の製造法。
JP55182010A 1980-12-24 1980-12-24 Semiconductor device and manufacture thereof Granted JPS57106140A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55182010A JPS57106140A (en) 1980-12-24 1980-12-24 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55182010A JPS57106140A (en) 1980-12-24 1980-12-24 Semiconductor device and manufacture thereof

Publications (2)

Publication Number Publication Date
JPS57106140A JPS57106140A (en) 1982-07-01
JPS6322464B2 true JPS6322464B2 (ja) 1988-05-12

Family

ID=16110741

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55182010A Granted JPS57106140A (en) 1980-12-24 1980-12-24 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS57106140A (ja)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3057832B2 (ja) * 1991-08-28 2000-07-04 日本電気株式会社 半導体装置
US5455195A (en) * 1994-05-06 1995-10-03 Texas Instruments Incorporated Method for obtaining metallurgical stability in integrated circuit conductive bonds
JP4754763B2 (ja) * 2000-09-12 2011-08-24 ローム株式会社 半導体装置
JP3514314B2 (ja) 2001-07-25 2004-03-31 ローム株式会社 半導体装置およびその製造方法
US7759803B2 (en) 2001-07-25 2010-07-20 Rohm Co., Ltd. Semiconductor device and method of manufacturing the same
JP4740536B2 (ja) * 2003-11-26 2011-08-03 ローム株式会社 半導体装置およびその製造方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4847273A (ja) * 1971-10-15 1973-07-05
JPS528785A (en) * 1975-07-10 1977-01-22 Citizen Watch Co Ltd Semiconductor device electrode structure

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4847273A (ja) * 1971-10-15 1973-07-05
JPS528785A (en) * 1975-07-10 1977-01-22 Citizen Watch Co Ltd Semiconductor device electrode structure

Also Published As

Publication number Publication date
JPS57106140A (en) 1982-07-01

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