JPS63187639A - 半導体装置 - Google Patents
半導体装置Info
- Publication number
- JPS63187639A JPS63187639A JP62018367A JP1836787A JPS63187639A JP S63187639 A JPS63187639 A JP S63187639A JP 62018367 A JP62018367 A JP 62018367A JP 1836787 A JP1836787 A JP 1836787A JP S63187639 A JPS63187639 A JP S63187639A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- wire
- external terminal
- semiconductor device
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 104
- 239000012212 insulator Substances 0.000 claims abstract description 9
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 3
- 239000011347 resin Substances 0.000 abstract description 6
- 229920005989 resin Polymers 0.000 abstract description 6
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 17
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 238000007789 sealing Methods 0.000 description 4
- 239000010949 copper Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- BERDEBHAJNAUOM-UHFFFAOYSA-N copper(I) oxide Inorganic materials [Cu]O[Cu] BERDEBHAJNAUOM-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- KRFJLUBVMFXRPN-UHFFFAOYSA-N cuprous oxide Chemical compound [O-2].[Cu+].[Cu+] KRFJLUBVMFXRPN-UHFFFAOYSA-N 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 229920002803 thermoplastic polyurethane Polymers 0.000 description 1
Classifications
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
め要約のデータは記録されません。
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置、特に、ボンディングワイヤを使
用する半導体装置に適用して有効な技術に関するもので
ある。
用する半導体装置に適用して有効な技術に関するもので
ある。
DILP、LCC等の樹脂封止型半導体装置は、半導体
チップの外部端子(ポンディングパッド)とインナーリ
ートとをワイヤで接続している。ワイヤは、ポールボン
ディング法或は超音波ボンディング法で形成される。前
記半導体チ・ツブ、インナーリート及びワイヤは、樹脂
封止部材(レジン)で封止されている。
チップの外部端子(ポンディングパッド)とインナーリ
ートとをワイヤで接続している。ワイヤは、ポールボン
ディング法或は超音波ボンディング法で形成される。前
記半導体チ・ツブ、インナーリート及びワイヤは、樹脂
封止部材(レジン)で封止されている。
なお、樹脂封止型半導体装置については、例えば、日経
マグロウヒル社、別冊rマイクロブへイセズJNo、2
.1984年6月11日発行、p82〜p’12に記載
されている。
マグロウヒル社、別冊rマイクロブへイセズJNo、2
.1984年6月11日発行、p82〜p’12に記載
されている。
しかしながら1本発明者は、前述の樹脂封止型半導体装
置について検討した結果、次の問題点が生じることを見
出した。
置について検討した結果、次の問題点が生じることを見
出した。
前述の樹脂封止型半導体装置は、半導体チップの外部端
子が配にされる近傍に、その外部端子の機能に対応する
インナーリートが配置されている。
子が配にされる近傍に、その外部端子の機能に対応する
インナーリートが配置されている。
例えば、半導体チップの基準電圧(接地電位)用外部端
子の近傍には、同一機能である基準電圧用リードが配置
されている。このように構成される樹脂封止型半導体装
置は、一つのリードの配置位置(機能)が変更された場
合に、簡単にプリント配線板へ実装することができない
。つまり、リートの配置位置の変更は、それに対応する
半導体チップの外部端子の位置の変更、それに接続され
る配線。
子の近傍には、同一機能である基準電圧用リードが配置
されている。このように構成される樹脂封止型半導体装
置は、一つのリードの配置位置(機能)が変更された場
合に、簡単にプリント配線板へ実装することができない
。つまり、リートの配置位置の変更は、それに対応する
半導体チップの外部端子の位置の変更、それに接続され
る配線。
入力段回路及び出力段回路のレイアウトの変更を必要と
する。このリードの配置位置の変更は、多種少量化が進
むにつれて頻度が高くなっている。
する。このリードの配置位置の変更は、多種少量化が進
むにつれて頻度が高くなっている。
このため、樹脂封止型半導体装INのリードの機能を必
要に応じて簡単に変更することができないという問題が
生じる。
要に応じて簡単に変更することができないという問題が
生じる。
また、マイクロコンピュータの半導体チップを有する樹
脂封止型半導体装には、半導体チップの所定周辺部にタ
イミング信号発生回路が配置されている。タイミング信
号発生回路は、その専用外部端子の近傍に配置さ九でい
る。タイミング信号発生回路は、各回路のタイミング信
号を出力するように構成されている。
脂封止型半導体装には、半導体チップの所定周辺部にタ
イミング信号発生回路が配置されている。タイミング信
号発生回路は、その専用外部端子の近傍に配置さ九でい
る。タイミング信号発生回路は、各回路のタイミング信
号を出力するように構成されている。
しかしながら、タイミング発生回路が最適な位置に配置
されていないので、タイミング信号発生回路と各回路と
を接続する各配線の長さが異なる。
されていないので、タイミング信号発生回路と各回路と
を接続する各配線の長さが異なる。
このため、タイミング信号にずれが生じたり、タイミン
グ信号のす九を補正する回路が必要になるという問題が
生じる。
グ信号のす九を補正する回路が必要になるという問題が
生じる。
本発明の目的は、半導体チップの外部端子とリード又は
半導体チップ塔載用基板の配線とをワイヤで接続する半
導体装置において、前記リード又は配線の機能を必要に
応じて簡単に変更することが可能な技術を提供すること
にある。
半導体チップ塔載用基板の配線とをワイヤで接続する半
導体装置において、前記リード又は配線の機能を必要に
応じて簡単に変更することが可能な技術を提供すること
にある。
本発明の他の目的は、半導体装置の半導体チップに形成
される回路を最適な位置に配置することが可能な技術を
提供することにある。
される回路を最適な位置に配置することが可能な技術を
提供することにある。
本発明の他の目的は、半導体装置の半導体チップの電源
配線に発生するノイズを低減することが可能な技術を提
供することにある。
配線に発生するノイズを低減することが可能な技術を提
供することにある。
本発明の他の目的は、前記夫々の目的を達成すると共に
、前記ワイヤ間の短絡、半導体チップとワイヤとの短絡
を防止することが可能な技術を提供することにある。
、前記ワイヤ間の短絡、半導体チップとワイヤとの短絡
を防止することが可能な技術を提供することにある。
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述及び添付図面によって明らかになるであろ
う。
明細書の記述及び添付図面によって明らかになるであろ
う。
本願において開示される発明のうち、代表的なものの概
要を説明すれば、下記のとおりである。
要を説明すれば、下記のとおりである。
半導体装置の半導体チップの外部端子とリート又は半導
体チップ塔載用基板の配線とを、被覆ワイヤをその他の
被覆ワイヤと交差させて接続する。
体チップ塔載用基板の配線とを、被覆ワイヤをその他の
被覆ワイヤと交差させて接続する。
また、半導体装置の半導体チップの所定外部端子を半導
体チップの中央部に構成し、この中央部に構成された外
部端子に被覆ワイヤを接続すると共に、被覆ワイヤの他
端をリード又は半導体チップ塔載用基板の配線に接続す
る。
体チップの中央部に構成し、この中央部に構成された外
部端子に被覆ワイヤを接続すると共に、被覆ワイヤの他
端をリード又は半導体チップ塔載用基板の配線に接続す
る。
上記した手段によれば、前記半導体チップの外部端子の
配置を変更することなく、リード又は配線の機能を必要
に応じて簡単に変更できる。
配置を変更することなく、リード又は配線の機能を必要
に応じて簡単に変更できる。
また、半導体装置の半導体チップに形成される回路、例
えばタイミング発生回路を最適な位置に配置し、タイミ
ング発生回路と各回路とを接続する配線長を均一にする
ことができる。
えばタイミング発生回路を最適な位置に配置し、タイミ
ング発生回路と各回路とを接続する配線長を均一にする
ことができる。
以下、本発明の構成について、実施例とともに説明する
。
。
なお、全図において、同一の機能を有するものは同一の
符号を付け、その繰り返しの説明は省略する。
符号を付け、その繰り返しの説明は省略する。
本発明の実施例Iである樹脂封止型半導体装置の概略構
成を第1図(断面図)で示し、樹脂封止型半導体装置の
要部を第2図(第1図の要部拡大断面図)で示す。
成を第1図(断面図)で示し、樹脂封止型半導体装置の
要部を第2図(第1図の要部拡大断面図)で示す。
第1図に示すように、樹脂封止型半導体装置1は、半導
体チップ2とリード3のインナーリード部3Aとを被覆
ワイヤ4で接続し、これらを樹脂封止部材5で封止して
いる。
体チップ2とリード3のインナーリード部3Aとを被覆
ワイヤ4で接続し、これらを樹脂封止部材5で封止して
いる。
前記半導体チップ2は、第2図に示すように、接続金属
膜6を介在させてタブ部3Cの上部に塔載されている。
膜6を介在させてタブ部3Cの上部に塔載されている。
半導体チップ2のパッシベーション膜2Bの間口部から
露出する外部端子(ポンディングパッド)2Aには、被
覆ワイヤ4の一端部が接続されている。被覆ワイヤ4の
他端部は、前述のようにインナーリード部3Aに接続さ
れている。 前記外部端子2Aは、例えばアルミニウム
膜或は所定の添加物が含有されたアルミニウム膜で形成
する。前記アウターリード部3Bは、樹脂封止部材5か
ら突出しており、プリント配線基板に形成される配LA
(端子)に半田等で接続されるように構成されている。
露出する外部端子(ポンディングパッド)2Aには、被
覆ワイヤ4の一端部が接続されている。被覆ワイヤ4の
他端部は、前述のようにインナーリード部3Aに接続さ
れている。 前記外部端子2Aは、例えばアルミニウム
膜或は所定の添加物が含有されたアルミニウム膜で形成
する。前記アウターリード部3Bは、樹脂封止部材5か
ら突出しており、プリント配線基板に形成される配LA
(端子)に半田等で接続されるように構成されている。
前記被覆ワイヤ4は、金属線4Aの表面に絶縁体4Bを
被覆して構成されている。金属線4Aは。
被覆して構成されている。金属線4Aは。
例えば金(Au)、銅(Cu)、アルミニウム(AQ)
で形成する。絶縁体4Bは1例えばウレタン樹脂。
で形成する。絶縁体4Bは1例えばウレタン樹脂。
ポリイミド樹脂、全屈酸化膜(Cub、Cu2O。
A Q 202 )で形成する。
このように構成される樹脂封止型半導体装置1は、第3
図(要部斜視図)で示すように1部分的に、半導体チッ
プ2の外部端子2Aとインナーリー+<部3Aとを、被
覆ワイヤ4をその他の被覆ワイヤ4と交差させて接続し
ている。基本的には、外部端子2Aが配置される近傍に
、その機能に対応したインナーリード部3Aを配置して
いる。このうち、例えば、基準電圧(接地電位GND)
用リード3の配置位置(機能)と電g’a圧(回路の動
作電位Vcc)用リート3の配置位置(4!i能)とを
変更する場合に、前記被覆ワイヤ4を交差させて、基準
電圧用外部端子2A、m源電圧用外部端子2Aの夫々に
接続している。この被覆ワイヤ4の交差は、外部端子2
Aの配置位置を変更せずに行われている。
図(要部斜視図)で示すように1部分的に、半導体チッ
プ2の外部端子2Aとインナーリー+<部3Aとを、被
覆ワイヤ4をその他の被覆ワイヤ4と交差させて接続し
ている。基本的には、外部端子2Aが配置される近傍に
、その機能に対応したインナーリード部3Aを配置して
いる。このうち、例えば、基準電圧(接地電位GND)
用リード3の配置位置(機能)と電g’a圧(回路の動
作電位Vcc)用リート3の配置位置(4!i能)とを
変更する場合に、前記被覆ワイヤ4を交差させて、基準
電圧用外部端子2A、m源電圧用外部端子2Aの夫々に
接続している。この被覆ワイヤ4の交差は、外部端子2
Aの配置位置を変更せずに行われている。
このように構成される樹脂封止型半導体装置1は、半導
体チップ2の外部端子2Δの配置を変更することなく、
リード3の配置(機能)を必要に応じて簡単に変更でき
る。つまり、リード3の配置の変更は、半導体チップ2
の外部端子2Aの配置の変更や、外部端子2人に接続さ
れる配線(アルミニウム配線)、入力段回路又は出力段
回路のレイアウトを変更する必要がない。
体チップ2の外部端子2Δの配置を変更することなく、
リード3の配置(機能)を必要に応じて簡単に変更でき
る。つまり、リード3の配置の変更は、半導体チップ2
の外部端子2Aの配置の変更や、外部端子2人に接続さ
れる配線(アルミニウム配線)、入力段回路又は出力段
回路のレイアウトを変更する必要がない。
被覆ワイヤ4をその他の被覆ワイヤ4と交差した場合1
表面に絶縁体4Bが設けられているので、両者間が短絡
することがない9また。被覆ワイヤ4は、表面に絶縁体
4Bが設けられているので。
表面に絶縁体4Bが設けられているので、両者間が短絡
することがない9また。被覆ワイヤ4は、表面に絶縁体
4Bが設けられているので。
半導体チップ2やタブ部3Cと短絡することがなり)。
また、樹脂封止型半導体装置1は、被覆ワイヤ4が他の
被覆ワイヤ4や半導体チップ2と短絡しないので、半導
体チップ2とインナーリート部3Aとを充分に離隔する
ことができる。つまり、リード3のインナーリード部3
Aの密度を低減することができるので、リード3の本数
を増加することができ、樹脂封止型半導体装置1の多ピ
ン化を図ることができる。
被覆ワイヤ4や半導体チップ2と短絡しないので、半導
体チップ2とインナーリート部3Aとを充分に離隔する
ことができる。つまり、リード3のインナーリード部3
Aの密度を低減することができるので、リード3の本数
を増加することができ、樹脂封止型半導体装置1の多ピ
ン化を図ることができる。
本実施例■は、マイクロコンピュータ機能の半導体チッ
プを有する樹脂封止型半導体装置に本発明を適用した2
本発明の他の実施例である。
プを有する樹脂封止型半導体装置に本発明を適用した2
本発明の他の実施例である。
本発明の実施例nである樹脂封止型半導体装置の概略構
成を第4図(要部平面図)で示す。
成を第4図(要部平面図)で示す。
第4図に示すように5本実施例の樹脂封止型半導体装置
1の半導体チップ2は、マイクロコンピュータ機能を有
している。半導体チップ2は、主に、レジスタ(REG
ISTER) 2 a 、インターラブド(INTER
RllPT) 2 b 、マイクロコードROM (μ
mROM) 2 c 。
1の半導体チップ2は、マイクロコンピュータ機能を有
している。半導体チップ2は、主に、レジスタ(REG
ISTER) 2 a 、インターラブド(INTER
RllPT) 2 b 、マイクロコードROM (μ
mROM) 2 c 。
タイマー及びシリアルコミニケーションインターフェイ
ス(TIMER/5CI) 2 d 、タイマー(TI
MER) 2 e 。
ス(TIMER/5CI) 2 d 、タイマー(TI
MER) 2 e 。
RAM(RAM)2 f 、 E P ROM(EFR
OM)2 g 、タイミング信号発生回路(O5C)
2 hで構成されている。
OM)2 g 、タイミング信号発生回路(O5C)
2 hで構成されている。
前記タイミング信号発生回路2hは、半導体チップ2の
実質的に中央部に配置されている。タイミング信号発生
回路2hは、半導体チップ2の外部の外部機器例えば水
晶発振器の信号によって駆動するように構成されている
。タイミング信号発生回路2hは、半導体チップ2の各
回路のタイミング信号を発生するように構成されている
。タイミング信号発生回路2hは、例えば、マイクロコ
ートROM2e、RAM2f、EPROM2gの夫々の
デコーダ回路やデータ出力回路のタイミング信号を発生
するように構成されている。
実質的に中央部に配置されている。タイミング信号発生
回路2hは、半導体チップ2の外部の外部機器例えば水
晶発振器の信号によって駆動するように構成されている
。タイミング信号発生回路2hは、半導体チップ2の各
回路のタイミング信号を発生するように構成されている
。タイミング信号発生回路2hは、例えば、マイクロコ
ートROM2e、RAM2f、EPROM2gの夫々の
デコーダ回路やデータ出力回路のタイミング信号を発生
するように構成されている。
タイミング信号発生回路2hは、その近傍すなわち半導
体チップ2の中央部に設けられた外部端子2Cとリード
3のインナーリード部3Aとを被覆ワイヤ4で接続する
ことで、外部機器と接続されている。この外部端子2C
とインナーリード部3Aとを接続する被覆ワイヤ4は、
他の被覆ワイヤ4.外部端子2A又は他の回路と短絡す
ることがない。
体チップ2の中央部に設けられた外部端子2Cとリード
3のインナーリード部3Aとを被覆ワイヤ4で接続する
ことで、外部機器と接続されている。この外部端子2C
とインナーリード部3Aとを接続する被覆ワイヤ4は、
他の被覆ワイヤ4.外部端子2A又は他の回路と短絡す
ることがない。
このように、樹脂封止型半導体装置1において、タイミ
ング信号発生回路2hの外部端子2Cを半導体チップ2
の中央部に構成し、この中央部に構成された外部端子2
Cに被覆ワイヤ4を接続すると共に、被覆ワイヤ4の他
端をインナーリード部3Aに接続することにより、タイ
ミング信号発生回路2hを最適な位置に配置し、タイミ
ング信号発生回路2hと各回路とを接続する各配線(例
えばアルミニウム配りの長を均一にすることができる。
ング信号発生回路2hの外部端子2Cを半導体チップ2
の中央部に構成し、この中央部に構成された外部端子2
Cに被覆ワイヤ4を接続すると共に、被覆ワイヤ4の他
端をインナーリード部3Aに接続することにより、タイ
ミング信号発生回路2hを最適な位置に配置し、タイミ
ング信号発生回路2hと各回路とを接続する各配線(例
えばアルミニウム配りの長を均一にすることができる。
すなわち、各回路に入力するタイミング信号がずれたり
、又タイミング回路のずれを補正する回路が必要となら
ない。
、又タイミング回路のずれを補正する回路が必要となら
ない。
また1本発明は、第4図の下側に示すように、外部端子
2Aよりも半導体チップ2の内側の周辺部に、外部端子
2Aに対向して配置された外部端子2Dとインナーリー
ド部3Aとの接続が、外部端子2Aとインナーリート部
3Aとを接続する被覆ワイヤ4と短絡することなく、被
覆ワイヤ4で接続することができる。
2Aよりも半導体チップ2の内側の周辺部に、外部端子
2Aに対向して配置された外部端子2Dとインナーリー
ド部3Aとの接続が、外部端子2Aとインナーリート部
3Aとを接続する被覆ワイヤ4と短絡することなく、被
覆ワイヤ4で接続することができる。
本実施例■は、樹脂封止型半導体装置の半導体チップの
電源配線に発生するノイズを低減することが可能な、本
発明の他の実施例である。
電源配線に発生するノイズを低減することが可能な、本
発明の他の実施例である。
本発明の実施例■である樹脂封止型半導体装置の概略構
成を第5図(要部平面図)で示す。
成を第5図(要部平面図)で示す。
第5図に示すように、樹脂封止型半導体装置1の半導体
チップ2の周辺部には、電源配置2Eが延在している。
チップ2の周辺部には、電源配置2Eが延在している。
電源配線2Eは、詳細に図示していないが、基準電圧用
電源配線と電源電圧用電源配線とで構成されている。電
源配線2Eは、半導体チップ2の周辺部に設けられた入
力段回路や出力段回路(バッファ回路)、又は内部回路
の基準電圧、電源電圧の夫々を形成するように構成され
ている。電源配線2Eの延在する中央部分には、電源用
インナーリード部3Aと接続される被覆ワイヤ4が接続
されている。
電源配線と電源電圧用電源配線とで構成されている。電
源配線2Eは、半導体チップ2の周辺部に設けられた入
力段回路や出力段回路(バッファ回路)、又は内部回路
の基準電圧、電源電圧の夫々を形成するように構成され
ている。電源配線2Eの延在する中央部分には、電源用
インナーリード部3Aと接続される被覆ワイヤ4が接続
されている。
このように、電源配g2Eの中央部分に被覆ワイヤ4を
接続することにより、ノイズの引き貫き経路を短縮する
ことができるので、電源配線2Eに生じるノイズを即座
に低減することができる。
接続することにより、ノイズの引き貫き経路を短縮する
ことができるので、電源配線2Eに生じるノイズを即座
に低減することができる。
以上、本発明者によってなされた発明を、前記実施例に
基づき具体的に説明したが、本発明は、前記実施例に限
定されるものではなく、その要旨を逸脱しない範囲にお
いて、種々変形し得ることは勿論である。
基づき具体的に説明したが、本発明は、前記実施例に限
定されるものではなく、その要旨を逸脱しない範囲にお
いて、種々変形し得ることは勿論である。
例えば1本発明は、半導体チップの外部端子とリードと
を接続するセラミック封止型半導体装置に適用すること
ができる。
を接続するセラミック封止型半導体装置に適用すること
ができる。
また、本発明は、複数の半導体チップを半導体チップ塔
載用基板(マザーボード)に塔載し、半導体チップの外
部端子と半導体チップ塔級用基板の配線(端子)とをワ
イヤで接続する半導体装置に適用することができる。
載用基板(マザーボード)に塔載し、半導体チップの外
部端子と半導体チップ塔級用基板の配線(端子)とをワ
イヤで接続する半導体装置に適用することができる。
本願において開示される発明のうち、代表的なものによ
って得ることができる効果を簡単に説明すれば、次のと
おりである。
って得ることができる効果を簡単に説明すれば、次のと
おりである。
半導体装置のリート又は配線の機能を必要に応じて簡単
に変更することができる。
に変更することができる。
また、半導体装置の半導体チップに形成される回路、例
えばタイミング信号発生回路を最適な位置に配置し、タ
イミング信号発生回路と各回路とを接続する配線長を均
一にすることができる。
えばタイミング信号発生回路を最適な位置に配置し、タ
イミング信号発生回路と各回路とを接続する配線長を均
一にすることができる。
第1図は1本発明の実施例Iである樹脂封止型半導体装
置の概略構成を示す断面図、 第2図は、前記樹脂封止型半導体装置の要部を示す要部
拡大断面図、 第3図は、前記樹脂封止型半導体装置の要部斜視図、 第4図は、本発明の実施例■である樹脂封止型半導体装
置の概略構成を示す要部平面図。 第5図は、本発明の実施例IIIである樹脂封止型半導
体装置の概略構成を示す要部平面図である。 図中、l・・・樹脂封止型半導体装置、2・・・半導体
チップ、2A、2C,2D・・・外部端子、2h・・タ
イミング信号発生回路、3・・・リード、3A・・・イ
ンナーリード部、3B・・アウターリード部、4・・・
被覆ワイヤ、4A・・・金属線、4B・・・絶縁体、5
・・・樹脂封止部材である。 代理人 弁理士 小川勝男 パ≧\ +−′ 第1図 第4図
置の概略構成を示す断面図、 第2図は、前記樹脂封止型半導体装置の要部を示す要部
拡大断面図、 第3図は、前記樹脂封止型半導体装置の要部斜視図、 第4図は、本発明の実施例■である樹脂封止型半導体装
置の概略構成を示す要部平面図。 第5図は、本発明の実施例IIIである樹脂封止型半導
体装置の概略構成を示す要部平面図である。 図中、l・・・樹脂封止型半導体装置、2・・・半導体
チップ、2A、2C,2D・・・外部端子、2h・・タ
イミング信号発生回路、3・・・リード、3A・・・イ
ンナーリード部、3B・・アウターリード部、4・・・
被覆ワイヤ、4A・・・金属線、4B・・・絶縁体、5
・・・樹脂封止部材である。 代理人 弁理士 小川勝男 パ≧\ +−′ 第1図 第4図
Claims (1)
- 【特許請求の範囲】 1、半導体チップの外部端子とリード又は半導体チップ
塔載用基板上に形成される配線とをワイヤで接続する半
導体装置において、前記ワイヤを金属線表面に絶縁体を
被覆した被覆ワイヤで構成し、該被覆ワイヤの少なくと
も1本をそれに隣接する被覆ワイヤと交差させて、前記
半導体チップの外部端子とリード又は配線とを接続した
ことを特徴とする半導体装置。 2、前記被覆ワイヤの交差は、前記半導体チップの外部
端子の配置を変更することなく、前記リード又は配線の
機能を変更できるように構成されていることを特徴とす
る特許請求の範囲第1項に記載の半導体装置。 3、半導体チップの外部端子とリード又は半導体チップ
塔載用基板上に形成される配線とをワイヤで接続する半
導体装置において、前記所定の外部端子を半導体チップ
の中央部に構成し、前記ワイヤを金属線表面に絶縁体を
被覆した被覆ワイヤで構成し、該被覆ワイヤの一端を前
記半導体チップの中央部に構成された外部端子に接続す
ると共に、他端を前記リード又は配線に接続したことを
特徴とする半導体装置。 4、前記半導体チップはマイクロコンピュータであり、
前記中央部に配置される外部端子はタイミング発生回路
に接続される外部端子であることを特徴とする特許請求
の範囲第4項に記載の半導体装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62018367A JPS63187639A (ja) | 1987-01-30 | 1987-01-30 | 半導体装置 |
EP88300399A EP0276940A3 (en) | 1987-01-30 | 1988-01-19 | Semiconductor chip having external terminals connected to corresponding leads by wires |
KR1019880000601A KR880009433A (ko) | 1987-01-30 | 1988-01-26 | 반도체 장치 및 그 제조방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62018367A JPS63187639A (ja) | 1987-01-30 | 1987-01-30 | 半導体装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63187639A true JPS63187639A (ja) | 1988-08-03 |
Family
ID=11969732
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62018367A Pending JPS63187639A (ja) | 1987-01-30 | 1987-01-30 | 半導体装置 |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP0276940A3 (ja) |
JP (1) | JPS63187639A (ja) |
KR (1) | KR880009433A (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5037023A (en) * | 1988-11-28 | 1991-08-06 | Hitachi, Ltd. | Method and apparatus for wire bonding |
US5176310A (en) * | 1988-11-28 | 1993-01-05 | Hitachi, Ltd. | Method and apparatus for wire bond |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4959706A (en) * | 1988-05-23 | 1990-09-25 | United Technologies Corporation | Integrated circuit having an improved bond pad |
JP2844558B2 (ja) * | 1995-06-29 | 1999-01-06 | 信越ポリマー株式会社 | チップ状半導体素子装着用の配線回路基板およびその製造方法 |
US20040124545A1 (en) * | 1996-12-09 | 2004-07-01 | Daniel Wang | High density integrated circuits and the method of packaging the same |
WO1998026452A1 (en) * | 1996-12-09 | 1998-06-18 | Microbonds, Inc. | High density integrated circuits and the method of packaging the same |
US6049136A (en) * | 1998-06-03 | 2000-04-11 | Hewlett-Packard Company | Integrated circuit having unique lead configuration |
US6894398B2 (en) | 2001-03-30 | 2005-05-17 | Intel Corporation | Insulated bond wire assembly for integrated circuits |
US20040119172A1 (en) * | 2002-12-18 | 2004-06-24 | Downey Susan H. | Packaged IC using insulated wire |
US6992377B2 (en) | 2004-02-26 | 2006-01-31 | Freescale Semiconductor, Inc. | Semiconductor package with crossing conductor assembly and method of manufacture |
TWI503905B (zh) * | 2013-05-09 | 2015-10-11 | 矽品精密工業股份有限公司 | 打線結構 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3969752A (en) * | 1973-12-03 | 1976-07-13 | Power Hybrids, Inc. | Hybrid transistor |
JPS58137221A (ja) * | 1982-02-10 | 1983-08-15 | Hitachi Ltd | ワイヤボンデイング装置 |
-
1987
- 1987-01-30 JP JP62018367A patent/JPS63187639A/ja active Pending
-
1988
- 1988-01-19 EP EP88300399A patent/EP0276940A3/en not_active Withdrawn
- 1988-01-26 KR KR1019880000601A patent/KR880009433A/ko not_active Application Discontinuation
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5037023A (en) * | 1988-11-28 | 1991-08-06 | Hitachi, Ltd. | Method and apparatus for wire bonding |
US5110032A (en) * | 1988-11-28 | 1992-05-05 | Hitachi, Ltd., | Method and apparatus for wire bonding |
US5176310A (en) * | 1988-11-28 | 1993-01-05 | Hitachi, Ltd. | Method and apparatus for wire bond |
Also Published As
Publication number | Publication date |
---|---|
EP0276940A3 (en) | 1990-05-30 |
EP0276940A2 (en) | 1988-08-03 |
KR880009433A (ko) | 1988-09-15 |
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