JPH0595018A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

Info

Publication number
JPH0595018A
JPH0595018A JP25543291A JP25543291A JPH0595018A JP H0595018 A JPH0595018 A JP H0595018A JP 25543291 A JP25543291 A JP 25543291A JP 25543291 A JP25543291 A JP 25543291A JP H0595018 A JPH0595018 A JP H0595018A
Authority
JP
Japan
Prior art keywords
semiconductor device
inner lead
wire
pad
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25543291A
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English (en)
Inventor
Yuugo Koyama
裕吾 小山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP25543291A priority Critical patent/JPH0595018A/ja
Publication of JPH0595018A publication Critical patent/JPH0595018A/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/4805—Shape
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
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    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
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  • Wire Bonding (AREA)

Abstract

(57)【要約】 【目的】パッドとインナーリードに高低差をつけること
で、ワイヤに高低差をつけてワイヤ接触を防止すること
を実現する。 【構成】半導体素子１上の外部端子であるパッド２のと
なりあったもの同士に高低差を設け、またインナーリー
ド３の隣あったもの同士にも高低差をつけて、ワイヤ４
でパッドとインナーリードとを結線する。

Description

【発明の詳細な説明】
【０００１】
【産業上の利用分野】本発明は半導体装置の製造技術に
関し、特にパッドの面積の小さい半導体装置、隣合うパ
ッドの間隔の狭い半導体装置、或いは半導体素子チップ
とリードの半導体素子と接続される側（インナーリー
ド）とを接続するワイヤの長さが長い半導体装置の有効
な製造技術に関する。
【０００２】
【従来の技術】半導体装置の一製造方法として、集積回
路が形成された半導体素子上の入出力端子であるボンデ
ィングパッドとこれに対応したリードフレームの各イン
ナーリード部とを接続し、ついで各リードの先端部（ア
ウターリード）を残して射出成型機等によりプラスチッ
クなどで一体的に成型するものがある。その際、ボンデ
ィングパッドとインナーリードとの接続の一方式として
ワイヤ（導電性金属細線）を用いたものがある。
【０００３】上記のような半導体装置は高集積化、高機
能化等ニーズによる半導体素子のＩ／Ｏピン数（入出力
端子数）増大に伴い半導体装置自体の外部との入出力端
子数も増大する傾向にある。これに伴って半導体素子と
リードフレームとを接続するワイヤの本数も増大してゆ
く。従って半導体装置の基板実装密度は益々増大する傾
向にある。
【０００４】
【発明が解決しようとする課題】上記のような半導体装
置の方向性を踏まえると、半導体チップ上のパッド部分
の面積縮小化、隣合うパッド同士の間隔の縮小化、それ
に伴うインナーリード部分の隣合う者同士の間隔の縮小
化を進めなければならない。その際パッド部分とインナ
ーリード部分とを接続するワイヤの本数が増えるため、
接続後の樹脂封止の際のワイヤ同士の接触という問題が
生じる。また上記細密化に伴いワイヤのパッド部側の端
子部同士の接触という問題も生じてくる。以上のような
問題点は、基板実装の高密度化を妨げる大きな要因とな
り得る。
【０００５】
【課題を解決するための手段】本発明による半導体装置
の製造方法は、半導体装置のチップと半導体装置のチッ
プの周囲に配されたインナーリードと、半導体装置のチ
ップとインナーリードとをワイヤによりボンディングし
た後、樹脂封止した半導体装置において、半導体装置の
チップ上の回路の入出力端であるパッドとインナーリー
ドとをワイヤボンディングする際にワイヤの高低の差を
つけることを特徴とする。
【０００６】
【実施例】図１は本発明の一実施例を示す要部の図であ
る。１は半導体チップ、２は半導体チップ上の回路の外
部端子であるパッド電極、３はリードフレームのインナ
ーリード、４はパッドとインナーリードとを接続するワ
イヤである。また、図２に図１の半導体チップ上のパッ
ド部の断面図を示す。５は半導体チップ、６はパッド電
極、７はパッドとインナーリードとを接続するワイヤで
ある。半導体チップのパッド部に第一、二図で示す隣合
うパッドの高さが相異なるものを形成する。隣合うパッ
ドの高さが異なるため、半導体チップ上のパッド上にボ
ンディングされたワイヤの端子の隣合う者同士の高さも
異なってくる。
【０００７】図３は図１のインナーリードをチップ側上
方から見た図である。８はインナーリード、９はパッド
とインナーリードとを接続するワイヤ、１０はインナー
リードの横ずれを防ぐためのテープである。図３のよう
にインナーリードの先端部を一つおきに変形させ、隣合
うインナーリード同士の高さが相異なるようにする。隣
合うインナーリードの先端部の高さが相異なるためイン
ナーリードの先端部上にボンディングされたワイヤの端
子の隣合う者同士の高さも異なってくる。
【０００８】図２と図３を組み合わせたのが図１であ
る。高低差をつけた半導体チップ上のパッド部の高い方
と高低差をつけたインナーリード先端部の高い方とをワ
イヤで接続し、またパッド部の低い方とインナーリード
部の低い方とをワイヤで接続している。こうすることに
よりパッド部とインナーリードの先端部とを接続してい
るワイヤの両端子部の、それぞれ隣合う者同士に高低差
が生まれる。またパッド部とインナーリード部とを接続
しているワイヤ自体も両端子部の高低差のため、隣合う
もの同士に高低差が生まれている。
【０００９】
【発明の効果】従来はパッド部の構造が平面的であった
ため隣合うパッド部間隔が狭くなると隣合うパッド部上
のワイヤ端子同士が接触してしまう恐れがあった。また
隣合うパッド部間隔が狭くなりまた隣合うインナーリー
ド同士の間隔が狭くなるとワイヤ同士が接触してしまう
恐れがあった。本発明はパッド部とインナーリード部と
を接続するワイヤの隣合うもの同士に高低差をつけるこ
とでワイヤ同士、またワイヤ端子部同士の接触を防ぐ効
果がある。
【図面の簡単な説明】
【図１】本発明の半導体装置の製造方法の一実施例を示
す要部の図。
【図２】図１の半導体チップ上のパッド部の断面図。
【図３】図１のインナーリードをチップ側上方から見た
図。
【符号の説明】
１，５， 半導体チップ ２，６， パッド ３，８， インナーリード ４，７，９， ワイヤ １０， テープ

Claims (1)

    【特許請求の範囲】
  1. 【請求項１】半導体装置のチップと半導体装置のチップ
    の周囲に配されたインナーリードと、半導体装置のチッ
    プとインナーリードとをワイヤ（導電性金属細線）によ
    り接続（ボンディング）させたあと、樹脂封止した半導
    体装置において、半導体装置のチップ上の回路の入出力
    端であるパッドとインナーリードとをワイヤによりボン
    ディングする際にワイヤの高低の差をつけることを特徴
    とする半導体装置の製造方法。
JP25543291A 1991-10-02 1991-10-02 半導体装置の製造方法 Pending JPH0595018A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25543291A JPH0595018A (ja) 1991-10-02 1991-10-02 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25543291A JPH0595018A (ja) 1991-10-02 1991-10-02 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
JPH0595018A true JPH0595018A (ja) 1993-04-16

Family

ID=17278690

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25543291A Pending JPH0595018A (ja) 1991-10-02 1991-10-02 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPH0595018A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7868460B2 (en) 2006-12-07 2011-01-11 Samsung Electronics Co., Ltd. Semiconductor package and method of manufacturing the same
JP2021150513A (ja) * 2020-03-19 2021-09-27 株式会社東芝 半導体チップ及び半導体装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7868460B2 (en) 2006-12-07 2011-01-11 Samsung Electronics Co., Ltd. Semiconductor package and method of manufacturing the same
JP2021150513A (ja) * 2020-03-19 2021-09-27 株式会社東芝 半導体チップ及び半導体装置

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