JPS63177042U - - Google Patents

Info

Publication number
JPS63177042U
JPS63177042U JP1987066673U JP6667387U JPS63177042U JP S63177042 U JPS63177042 U JP S63177042U JP 1987066673 U JP1987066673 U JP 1987066673U JP 6667387 U JP6667387 U JP 6667387U JP S63177042 U JPS63177042 U JP S63177042U
Authority
JP
Japan
Prior art keywords
film carrier
circuit element
film
mounting surface
bonded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1987066673U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987066673U priority Critical patent/JPS63177042U/ja
Publication of JPS63177042U publication Critical patent/JPS63177042U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】
第１図は本考案に係るフイルムキヤリアの一実
施例を示す部分的横断面とＩＣチツプとを示す構
造図、第２図は従来のフイルムキヤリアの部分的
横断面とＩＣチツプとを示す構造図、第３図はフ
イルムキヤリアとＩＣチツプとのボンデイング作
業を説明するための説明図である。 １……フイルムベース、２……リード、３……
接着剤層、４，４′……金バンブ、５……ＩＣチ
ツプ、６……パツド、７……パツド保持層、８…
…絶縁層、９……ボンデイング・ツール。

Claims (1)

  1. 【実用新案登録請求の範囲】 (1) 絶縁性のベースフイルムと該フイルムの一
    面に接合された銅箔とバンブとから成り、且つ、
    半導体素子のような回路素子を取付け得るデバイ
    ス穴を有する可撓性のフイルムキヤリアにおいて
    、該フイルムキヤリアの回路素子取付面であつて
    、且つ、回路素子とボンデングする部分の近傍範
    囲の面上に、適宜材質の絶縁層を形成する如く構
    成したことを特徴とするフイルムキヤリア。 (2) 前記フイルムキヤリアの回路素子取付面は
    、インナーリード側部分に存在する個所にある面
    である実用新案登録請求の範囲第１項に記載のフ
    イルムキヤリアテープ。
JP1987066673U 1987-05-01 1987-05-01 Pending JPS63177042U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987066673U JPS63177042U (ja) 1987-05-01 1987-05-01

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987066673U JPS63177042U (ja) 1987-05-01 1987-05-01

Publications (1)

Publication Number Publication Date
JPS63177042U true JPS63177042U (ja) 1988-11-16

Family

ID=30904900

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987066673U Pending JPS63177042U (ja) 1987-05-01 1987-05-01

Country Status (1)

Country Link
JP (1) JPS63177042U (ja)

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