JPS6317243Y2 - - Google Patents

Info

Publication number
JPS6317243Y2
JPS6317243Y2 JP1983181254U JP18125483U JPS6317243Y2 JP S6317243 Y2 JPS6317243 Y2 JP S6317243Y2 JP 1983181254 U JP1983181254 U JP 1983181254U JP 18125483 U JP18125483 U JP 18125483U JP S6317243 Y2 JPS6317243 Y2 JP S6317243Y2
Authority
JP
Japan
Prior art keywords
wafer
mesa
cleavage
plane
sides
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1983181254U
Other languages
English (en)
Japanese (ja)
Other versions
JPS6088535U (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1983181254U priority Critical patent/JPS6088535U/ja
Priority to US06/673,400 priority patent/US4630093A/en
Publication of JPS6088535U publication Critical patent/JPS6088535U/ja
Application granted granted Critical
Publication of JPS6317243Y2 publication Critical patent/JPS6317243Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02021—Edge treatment, chamfering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02019—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02035—Shaping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54493—Peripheral marks on wafers, e.g. orientation flats, notches, lot number
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/161—Tapered edges
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/975—Substrate or mask aligning feature
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/21—Circular sheet or circular blank
    • Y10T428/219—Edge structure

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Dicing (AREA)
  • Weting (AREA)
JP1983181254U 1983-11-24 1983-11-24 半導体ウエハ Granted JPS6088535U (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP1983181254U JPS6088535U (ja) 1983-11-24 1983-11-24 半導体ウエハ
US06/673,400 US4630093A (en) 1983-11-24 1984-11-20 Wafer of semiconductors

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1983181254U JPS6088535U (ja) 1983-11-24 1983-11-24 半導体ウエハ

Publications (2)

Publication Number Publication Date
JPS6088535U JPS6088535U (ja) 1985-06-18
JPS6317243Y2 true JPS6317243Y2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1988-05-16

Family

ID=16097484

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1983181254U Granted JPS6088535U (ja) 1983-11-24 1983-11-24 半導体ウエハ

Country Status (2)

Country Link
US (1) US4630093A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS6088535U (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5230747A (en) * 1982-07-30 1993-07-27 Hitachi, Ltd. Wafer having chamfered bend portions in the joint regions between the contour of the wafer and the cut-away portion of the wafer
US5225235A (en) * 1987-05-18 1993-07-06 Osaka Titanium Co., Ltd. Semiconductor wafer and manufacturing method therefor
US4925809A (en) * 1987-05-23 1990-05-15 Osaka Titanium Co., Ltd. Semiconductor wafer and epitaxial growth on the semiconductor wafer with autodoping control and manufacturing method therefor
JPH0624179B2 (ja) * 1989-04-17 1994-03-30 信越半導体株式会社 半導体シリコンウェーハおよびその製造方法
JPH0624200B2 (ja) * 1989-04-28 1994-03-30 信越半導体株式会社 半導体デバイス用基板の加工方法
US5182233A (en) * 1989-08-02 1993-01-26 Kabushiki Kaisha Toshiba Compound semiconductor pellet, and method for dicing compound semiconductor wafer
FR2681472B1 (fr) * 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
US5918029A (en) * 1996-09-27 1999-06-29 Digital Equipment Corporation Bus interface slicing mechanism allowing for a control/data-path slice
DE4414373C2 (de) * 1994-04-25 1998-05-20 Siemens Ag Halbleiter-Wafer mit bearbeiteten Kanten
FR2748851B1 (fr) * 1996-05-15 1998-08-07 Commissariat Energie Atomique Procede de realisation d'une couche mince de materiau semiconducteur
FR2773261B1 (fr) 1997-12-30 2000-01-28 Commissariat Energie Atomique Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions
FR2823599B1 (fr) 2001-04-13 2004-12-17 Commissariat Energie Atomique Substrat demomtable a tenue mecanique controlee et procede de realisation
US7258931B2 (en) * 2002-08-29 2007-08-21 Samsung Electronics Co., Ltd. Semiconductor wafers having asymmetric edge profiles that facilitate high yield processing by inhibiting particulate contamination
FR2848336B1 (fr) 2002-12-09 2005-10-28 Commissariat Energie Atomique Procede de realisation d'une structure contrainte destinee a etre dissociee
JP3580311B1 (ja) * 2003-03-28 2004-10-20 住友電気工業株式会社 表裏識別した矩形窒化物半導体基板
FR2856844B1 (fr) 2003-06-24 2006-02-17 Commissariat Energie Atomique Circuit integre sur puce de hautes performances
JP2005026413A (ja) * 2003-07-01 2005-01-27 Renesas Technology Corp 半導体ウエハ、半導体素子およびその製造方法
FR2857953B1 (fr) 2003-07-21 2006-01-13 Commissariat Energie Atomique Structure empilee, et procede pour la fabriquer
FR2861497B1 (fr) 2003-10-28 2006-02-10 Soitec Silicon On Insulator Procede de transfert catastrophique d'une couche fine apres co-implantation
FR2889887B1 (fr) 2005-08-16 2007-11-09 Commissariat Energie Atomique Procede de report d'une couche mince sur un support
FR2891281B1 (fr) 2005-09-28 2007-12-28 Commissariat Energie Atomique Procede de fabrication d'un element en couches minces.
TWI314758B (en) * 2006-04-20 2009-09-11 Touch Micro System Tech Wafer having an asymmetric edge profile and method of making the same
FR2910179B1 (fr) 2006-12-19 2009-03-13 Commissariat Energie Atomique PROCEDE DE FABRICATION DE COUCHES MINCES DE GaN PAR IMPLANTATION ET RECYCLAGE D'UN SUBSTRAT DE DEPART
US8389099B1 (en) 2007-06-01 2013-03-05 Rubicon Technology, Inc. Asymmetrical wafer configurations and method for creating the same
FR2925221B1 (fr) 2007-12-17 2010-02-19 Commissariat Energie Atomique Procede de transfert d'une couche mince
CN101354228B (zh) * 2008-09-24 2010-06-09 友达光电股份有限公司 基板辨识治具与基板的辨识方法
FR2947098A1 (fr) 2009-06-18 2010-12-24 Commissariat Energie Atomique Procede de transfert d'une couche mince sur un substrat cible ayant un coefficient de dilatation thermique different de celui de la couche mince
JP1441120S (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * 2010-08-17 2015-05-11
USD651991S1 (en) * 2010-08-17 2012-01-10 Sumitomo Electric Industries, Ltd. Semiconductor substrate
CA138031S (en) * 2010-08-17 2011-11-17 Sumitomo Electric Industries Semiconductor substrate
CN113307471A (zh) * 2015-07-24 2021-08-27 Ａｇｃ株式会社 玻璃基板、捆包体以及玻璃基板的制造方法
JP1563718S (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * 2015-12-28 2016-11-21
JP1563719S (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * 2015-12-28 2016-11-21
USD940131S1 (en) * 2019-07-29 2022-01-04 Samsung Display Co., Ltd. Display panel
USD966276S1 (en) 2019-07-29 2022-10-11 Samsung Display Co., Ltd. Display module for wearable device
USD958094S1 (en) * 2019-07-29 2022-07-19 Samsung Display Co., Ltd. Display panel
US11482408B2 (en) * 2020-06-23 2022-10-25 Disco Corporation Method of processing wafer

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS506296U (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * 1973-05-14 1975-01-22
DE2358937C3 (de) * 1973-11-27 1976-07-15 Licentia Gmbh Thyristor fuer hochspannung im kilovoltbereich
JPS6058579B2 (ja) * 1977-07-25 1985-12-20 日本電気株式会社 半導体ウエ−ハの製造方法
JPS5515217A (en) * 1978-07-18 1980-02-02 Chiyou Lsi Gijutsu Kenkyu Kumiai Working method for semiconductor and its working apparatus
JPS5823430A (ja) * 1981-08-04 1983-02-12 Nec Kyushu Ltd 半導体ウエハ−ス
JPS5825039A (ja) * 1981-08-05 1983-02-15 Hitachi Ltd 電子銃構体
JPS58103144A (ja) * 1981-12-15 1983-06-20 Matsushita Electronics Corp 半導体装置

Also Published As

Publication number Publication date
JPS6088535U (ja) 1985-06-18
US4630093A (en) 1986-12-16

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