JPS63149568U - - Google Patents

Info

Publication number
JPS63149568U
JPS63149568U JP4251387U JP4251387U JPS63149568U JP S63149568 U JPS63149568 U JP S63149568U JP 4251387 U JP4251387 U JP 4251387U JP 4251387 U JP4251387 U JP 4251387U JP S63149568 U JPS63149568 U JP S63149568U
Authority
JP
Japan
Prior art keywords
thick film
integrated circuit
hybrid integrated
conductive pattern
film hybrid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4251387U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP4251387U priority Critical patent/JPS63149568U/ja
Publication of JPS63149568U publication Critical patent/JPS63149568U/ja
Pending legal-status Critical Current

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  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の第1実施例を示す平面図、第
2図は同断面図、第3図は第2実施例を示す平面
図、第4図は同断面図、第5図はパワートランジ
スタを示す平面図、第6図は同断面図である。 2……回路基板、3,4,5,6……導電パタ
ーン、7……パワートランジスタ(電子部品)、
9……誘電体ペースト(絶縁層)、C……コレク
タ電極(導電部)。
Fig. 1 is a plan view showing the first embodiment of the present invention, Fig. 2 is a sectional view thereof, Fig. 3 is a plan view showing the second embodiment, Fig. 4 is a sectional view thereof, and Fig. 5 is a power A plan view showing the transistor, and FIG. 6 is a sectional view thereof. 2... Circuit board, 3, 4, 5, 6... Conductive pattern, 7... Power transistor (electronic component),
9... Dielectric paste (insulating layer), C... Collector electrode (conductive part).

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 所定の導電パターンを形成した回路基板に、表
面に導電部を有する電子部品を実装する厚膜混成
集積回路において、前記導電パターン上における
前記導電部の載置位置に絶縁層を積層形成するこ
とを特徴とする厚膜混成集積回路。
In a thick film hybrid integrated circuit in which an electronic component having a conductive part on the surface is mounted on a circuit board on which a predetermined conductive pattern is formed, an insulating layer is laminated at the position where the conductive part is placed on the conductive pattern. Characteristic thick film hybrid integrated circuit.
JP4251387U 1987-03-23 1987-03-23 Pending JPS63149568U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4251387U JPS63149568U (en) 1987-03-23 1987-03-23

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4251387U JPS63149568U (en) 1987-03-23 1987-03-23

Publications (1)

Publication Number Publication Date
JPS63149568U true JPS63149568U (en) 1988-10-03

Family

ID=30858497

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4251387U Pending JPS63149568U (en) 1987-03-23 1987-03-23

Country Status (1)

Country Link
JP (1) JPS63149568U (en)

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